1:8 LVDS Output 1.8V Fanout Buffer
IDT8P34S1208I
DATA SHEET
General Description
The IDT8P34S1208I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1208I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1208I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
Eight low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
Maximum input clock frequency: 1.2GHz (maximum)
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 20ps (typical)
Propagation delay: 315ps (typical)
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz - 20MHz: 41fs (typical)
Full 1.8V supply voltage
Lead-free (RoHS 6), 28-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram.
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pin Assignment
21
20
19
18
17
16
15
14
GND
13
nQ0
12
Q0
11
V
REF0
V
REF0
V
DD
Voltage
Reference
Q4
22
nQ4
23
Q5
24
nQ5
25
nQ6
27
V
DD
28
1
IDT8P34S1208I
28-lead VFQFN
5.0mm x 5.0mm x 0.75mm
package body
NB Package
Top View
2
3
4
5
6
7
CLK0
nCLK0
3.25mm x 3.25mm ePad Size
10
Q6
26
nCLK0
9
CLK0
8
V
DD
f
REF
V
DD
CLK1
nCLK1
SEL
Voltage
Reference
V
REF1
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
1
©2014 Integrated Device Technology, Inc.
nCLK1
V
REF1
GND
CLK1
SEL
Q7
nQ7
V
DD
nQ3
nQ2
nQ1
Q3
Q2
Q1
IDT8P34S1208I Data Sheet
1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Note 1.
Number
1, 14
2, 3
4
5
6
Name
GND
Q7, nQ7
SEL
CLK1
nCLK1
Power
Output
Input
Input
Input
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Power supply pin.
Differential output pair 7. LVDS interface levels.
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
Non-inverting differential clock/data input 1.
Inverting differential clock/data input 1. V
DD
/2 default when left floating.
Bias voltage reference. Provides an input bias voltage for the CLK1, nCLK1
input pair in AC-coupled applications. Refer to
Figures 2B and 2C
for
applicable AC-coupled input interfaces.
Power supply pin.
Pulldown
Pullup/
Pulldown
Non-inverting differential clock/data input 0.
Inverting differential clock/data input 0. V
DD
/2 default when left floating.
Bias voltage reference. Provides an input bias voltage for the CLK0, nCLK0
input pair in AC-coupled applications. Refer to
Figures 2B and 2C
for
applicable AC-coupled input interfaces.
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
Differential output pair 2. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
Differential output pair 4. LVDS interface levels.
Differential output pair 5. LVDS interface levels.
Differential output pair 6. LVDS interface levels.
7
8, 15, 28
9
10
V
REF1
V
DD
CLK0
nCLK0
Output
Power
Input
Input
11
12, 13
16, 17
18, 19
20, 21
22, 23
24, 25
26, 27
1.
V
REF0
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3. SEL Input Function Table
Note 1.
Input
SEL
0
1
1.
Operation
CLK0, nCLK0 is the selected differential clock input.
CLK1, nCLK1 is the selected differential clock input.
SEL is an asynchronous control.
2
©2014 Integrated Device Technology, Inc.
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
IDT8P34S1208I Data Sheet
1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
NOTE 1: According to JEDEC JS-001-2012/JESD22-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±2mA
125°C
-65°C to 150°C
2000V
1500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Q0 to Q7 terminated 100 between nQx, Qx
Test Conditions
Minimum
1.71
Typical
1.8
120
Maximum
1.89
140
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL
SEL
V
DD
= V
IN
= 1.89V
V
DD
= 1.89V, V
IN
= 0V
-10
Test Conditions
Minimum
V
DD
* 0.65
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
* 0.35
150
Units
V
V
µA
µA
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
3
©2014 Integrated Device Technology, Inc.
IDT8P34S1208I Data Sheet
1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
Table 4C. Differential Inputs Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input
High Current
Input
Low Current
CLK0, nCLK0,
CLK1, nCLK1
CLK0, CLK1
nCLK0, nCLK1
Test Conditions
V
IN
= V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
I
REF
= +100µA, V
DD
= 1.8V
V
DD
= 1.89V
-10
-150
0.9
0.2
0.9
1.30
1.0
V
DD
– (V
PP
/2)
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
I
IL
V
REF
V
PP
V
CMR
1.
2.
3.
Reference Voltage for Input
Bias
Note 1.
Peak-to-Peak Voltage
Note3.
Common Mode Input
Voltage
Note 2. Note 3.
V
REF
specification is applicable to the AC-coupled input interfaces shown in
Figures 2B and 2C.
Common mode input voltage is defined as crosspoint voltage.
V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
Table 4D. LVDS DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.0
1.23
Test Conditions
outputs loaded with 100
Minimum
247
Typical
350
Maximum
454
50
1.4
50
Units
mV
mV
V
mV
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
4
©2014 Integrated Device Technology, Inc.
IDT8P34S1208I Data Sheet
1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Electrical Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°
Note 1.
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(i)
tsk(p)
tsk(pp)
Parameter
Input
Frequency
Input
Edge Rate
CLK[0:1],
nCLK[0:1]
CLK[0:1],
nCLK[0:1]
CLK[0:1]; nCLK[0:1] to any Qx, nQx
for V
PP
= 0.4V
1.5
190
315
20
10
f
REF
= 100MHz
6
400
40
45
20
250
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
10% to 90%
outputs loaded with 100
t
R
/ t
F
Output Rise/ Fall Time
20% to 80%
outputs loaded with 100
Mux Isolation
Note 6.
f
REF
= 100MHz
175
80
260
ps
dB
122
88
84
57
41
41
55
40
40
305
221
110
110
107
78
78
112
85
85
400
Test Conditions
Minimum
Typical
Maximum
1.2
Units
GHz
V/ns
ps
ps
ps
ps
ps
fs
fs
fs
fs
fs
fs
fs
fs
fs
ps
Propagation Delay
Note 2.
Output Skew
Note 3. Note 4.
Input Skew
Pulse Skew
Part-to-Part Skew
Note 5.
t
JIT
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
MUX
ISOLATION
1.
2.
3.
4.
5.
6.
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-
librium has been reached under these conditions.
Measured from the differential input crossing point to the differential output crossing point
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
This parameter is defined in accordance with JEDEC Standard 65.
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Qx, nQx outputs measured differentially. See
MUX Isolation diagram
in the
Parameter Measurement Information section.
5
©2014 Integrated Device Technology, Inc.
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
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