ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART
3:1 Active HDMI 1.3 Compatible Switch with Optimized
Equalization for Enhanced Signal Integrity
Features
• Supply voltage, V
CC
= 3.3V ±5%
• Each Port is compatible w/ DVI, HDMI 1.1, HDMI 1.2 or
HDMI 1.3 signals
• Supports both AC-coupled and DC-coupled inputs
• Support for 8-bit, 10-bit, and 12-bit deep color per channel
• High Performance, up to 2.5 Gbps per channel
• Switching support for 3 side band signals
(SCL, SDA and HPD)
• 5V Tolerance on all side band signals
• SCL, SDA, and HPD pins are the only pins that can support
HOT INSERTION
• Integrated 50-ohm
(±10%)
termination resistors at each high
speed signal input
• Configurable output swing control
(500mV, 750mV, 1000mV)
• Configurable Pre-Emphasis levels
(0dB, 1.5dB, 3.5dB, & 6.0dB)
• Configurable De-Emphasis
(0dB, -3.5dB, -6.0dB, -9.5dB)
• Optimized Equalization
Single default setting will support all cable lengths
• ESD protection = 8kV (typical) on high-speed data channels
only
• Propagation delay ≤ 2ns
• High Impedance Outputs when disabled
• Packaging (Pb-free & Green): 80-contact LQFP (FF80)
Description
Pericom Semiconductor’s PI3HDMI341ART 3:1 active switch
circuit is targeted for high-resolution video networks that are
based on DVI/HDMI standards and TMDS signal processing.
The PI3HDMI341ART is an active 3 TMDS to 1 TMDS receiver
switch with Hi-Z outputs. The device receives differential signals
from selected video components and drives the video display unit.
It provides three controllable output swings that can be controlled
through a single bit. The allowable output swings are 500mV,
750mV and 1000mV. This solution also provides a unique
advanced pre-emphasis technique to increase rise and fall times
which are reduced during transmission across long distances.
Each complete HDMI/DVI channel also has slower speed, side
band signals, that are required to be switched. Pericom’s solution
provides a complete solution by integrating the side band switch
together with the high speed switch in a single solution. Using
Equalization at the input of each of the high speed channels,
Pericom can successfully eliminate deterministic jitter caused by
long cables from the source to the sink. The elimination of the
deterministic jitter allows the user to use much longer cables (up
to 25 meters).
The maximum DVI/HDMI Bandwidth of 2.5 Gbps provides 12-
bit deep color support, which is offered by HDMI revision 1.3.
Due to its active uni-directional feature, this switch is designed
for usage only for the video receiver’s side. For consumer video
networks, the device sits at the receiver’s side to switch between
multiple video components, such as PC, DVD, STB, D-VHS,
etc. The PI3HDMI341ART is the industry’s first active DVI/
HDMI switch compatible with HDMI 1.1, 1.2, and 1.3 which
ensures transmitting high-bandwidth video streams from video
components to the display unit. The PI3HDMI341ART also
provides enhanced robust ESD/EOS protection of 8kV, which is
required by many consumer video networks today.
The Optimized Equalization provides the user a single optimal
setting that can provide HDMI compliance for all cable lengths:
1meter to 20meters and color depths of 8bit/ch, or 12bit/ch.
Pericom also offers the abiility to fine tune the equalization
settings in situations where cable length is known. For example,
if 25meter cable length is required, Pericom's solution can be
adjusted to 16dB EQ to accept 25metere cable length.
1
PS8883
01/05/07
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART
3:1 Active HDMI 1.3 Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Pin Description
Pin #
6,9,12,15
68, 71, 74, 77
49, 52, 55, 58
5, 8, 11, 14
67, 70, 73, 76
48, 51, 54, 57
4, 10, 16 24, 30, 36, 37, 47,
53, 59, 65, 66, 72, 78
80
62
44
40
Pin Name
A11, A12, A13, A14
A21, A22, A23, A24
A31, A32, A33, A34
B11, B12, B13, B14
B21, B22, B23, B24
B31, B32, B33, B34
GND
HPD1
HPD2
HPD3
HPD_Sink
O
O
O
I
I/O
I
I
I
I
I
I
Description
Port 1 TMDS Positive inputs
Port 2 TMDS Positive inputs
Port 3 TMDS Positive inputs
Port 1 TMDS Negative inputs
Port 2 TMDS Negative inputs
Port 3 TMDS Negative inputs
Ground
Port 1 HPD output
Port 2 HPD output
Port 3 HPD output
Sink side hot plug detector input. High: 5-V power signal
asserted from source to sink and EDID is ready.
Low: No 5-V power signal asserted from source to sink, or
EDID is not ready.
Output Enable, Active LOW
Port 1 DDC Clock
Port 2 DDC Clock
Port 3 DDC Clock
Sink Side DDC Data
Port 1 DDC Data
Port 2 DDC Data
Port 3 DDC Data
Sink Side DDC Data
Source Input Selector
3.3V Power Supply
O
O
I
I
TMDS positive outputs
TMDS negative outputs
Equalizer controls
(1)
Output buffer controls
Note: OC_S3 has an internal pull-up resistor. OC_S2 has an
internal pull-down resistor.
42
3
64
46
38
2
63
45
39
21,22,23
7, 13, 17 27, 33, 43, 50, 56
61, 69, 75, 79
34, 31, 28, 25
35, 32, 29, 26
41, 60
19, 18, 20, 1
OE
SCL1
SCL2
SCL3
SCL_Sink
SDA1
SDA2
SDA3
SDA_Sink
S1, S2, S3
V
CC
Y1, Y2, Y3, Y4
Z1, Z2, Z3, Z4
EQ_S0, EQ_S1
OC_S0, OC_S1,
OC_S2, OC_S3
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Note:
1. EQ_S0 has an internal pull-down and EQ_S1 has an internal pull-up
3
PS8883
01/05/07
京公网安备 11010802033920号
EEWORLD
