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71V67703S85PFGI

Description
SRAM 9M 3.3V PBSRAM SLOW F/T
Categorystorage   
File Size170KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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71V67703S85PFGI Overview

SRAM 9M 3.3V PBSRAM SLOW F/T

71V67703S85PFGI Parametric

Parameter NameAttribute value
Product CategorySRAM
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Memory Size9 Mbit
Organization256 k x 36
Access Time8.5 ns
Maximum Clock Frequency87 MHz
Interface TypeParallel
Supply Voltage - Max3.465 V
Supply Voltage - Min3.135 V
Supply Current - Max210 mA
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseTQFP-100
PackagingTray
Height1.4 mm
Length20 mm
Memory TypeSDR
Moisture SensitiveYes
Operating Temperature Range- 40 C to + 85 C
Factory Pack Quantity72
TypeSynchronous
Width14 mm
Unit Weight0.023175 oz
256K X 36, 512K X 18
IDT71V67703
3.3V Synchronous SRAMs
IDT71V67903
3.3V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
Features
256K x 36, 512K x 18 memory configurations
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O supply (V
DDQ
)
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA)
Green parts available see ordering information
Functional Block Diagram
LBO
ADV
CEN
Burst
Sequence
INTERNAL
ADDRESS
CLK
ADSC
ADSP
CLK EN
ADDRESS
REGISTER
Byte 1
Write Register
Binary
Counter
CLR
2
Burst
Logic
18/19
A0*
A1*
Q0
Q1
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
2
A
0
,A
1
18/19
A
2 -
A
18
36/18
36/18
A
0–
A
17/18
GW
BWE
BW
1
Byte 1
Write Driver
9
Byte 2
Write Register
Byte 2
Write Driver
BW
2
Byte 3
Write Register
9
Byte 3
Write Driver
BW
3
Byte 4
Write Register
9
Byte 4
Write Driver
BW
4
9
CE
CS
0
CS
1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
OE
OE
I/O
0
–I/O
31
I/O
P1–
I/O
P4
36/18
OUTPUT
BUFFER
,
5309 drw 01
DECEMBER 2014
1
©2014 Integrated Device Technology, Inc.
DSC-5309/06
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