Revision 5
ex Automotive Family FPGAs
Specifications
•
•
•
•
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22
μm
CMOS Process Technology
Up to 132 User-Programmable I/O Pins
•
•
•
•
•
•
•
•
•
•
•
Live on Power-Up
No Power-Up/Down Sequence Required for Supply
Voltages
Configurable Weak Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power-Up
Individual Output Slew-Rate Control
2.5 V and 3.3 V I/Os
Software Design Support with Designer and Libero
®
Integrated Design Environment (IDE) Tools
Up to 100% Resource Utilization with 100% Pin Locking
Deterministic Timing
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
FuseLock™ Secure Programming Technology Designed
to Prevent Reverse Engineering and Design Theft
Features
•
•
•
•
•
•
250 MHz Internal Performance, Low-Power Antifuse
FPGA
Advanced Small-Footprint Packages
Pin-to-Pin Compatibility with eX Commercial- and
Industrial-Grade Devices
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
Product Profile
Device
Capacity
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Combinatorial Cells
Maximum User I/Os
Global Clocks
Hardwired
Routed
Speed Grades*
Temperature Grades*
Package
(by pin count)
TQ
CS
3,000
2,000
6,000
4,000
12,000
8,000
eX64
eX128
eX256
64
128
128
84
1
2
Std.
A
64, 100
49, 128
128
256
256
100
1
2
Std.
A
64, 100
49, 128
256
512
512
132
1
2
Std.
A
100
128, 180
Note:
* The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to
the
eX Family FPGAs
datasheet for more details.
October 2012
© 2012 Microsemi Corporation
i
Ordering Information
eX128
TQ
G
100
A
Application (Ambient Temperature Range)
A = Automotive (-40°C to 125°C)
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
TQ = Thin Quad Flat Pack (1.4mm pitch)
CS = Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank= Standard Speed
P = Approximately 30% Faster than Standard
F = Approximately 40% Slower than Standard
Part Number
eX64 = 64 Dedicated Flip-Flops (3,000 System Gates)
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Note:
Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based
on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If
testing to ensure guaranteed operation at extended temperatures is required, please contact your local Microsemi SoC
Products Group Sales office to discuss testing options available.
Plastic Device Resources
User I/Os (Including Clock Buffers)
Device
eX64
eX128
eX256
TQ 64
41
46
–
TQ100
56
70
81
CS49
36
36
–
CS128
84
100
100
CS180
–
–
132
Note:
Package Definitions:TQ
= Thin Quad Flat Pack, CS = Chip Scale Package
Speed Grade and Temperature Grade Matrix
Std.
A
✓
Note:
Refer to the
eX Family FPGAs
datasheet for more details on commercial- and industrial-grade offerings.
Contact your local Microsemi SoC Products Group representative for device availability.
ii
R ev i si o n 5
ex Automotive Family FPGAs
Table of Contents
ex Automotive Family FPGAs
ex Automotive Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
2.5 V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
CEQ Values for eX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Package Pin Assignments
TQ64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
TQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
CS49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
CS128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
CS180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Revision 5
iii
1 – ex Automotive Family FPGAs
General Description
Based on a 0.22 µm CMOS process technology, the eX family of FPGAs is a low-cost solution for low-
power, high-performance designs. With the automotive temperature grade support (–40ºC to 125ºC), the
eX devices can address many in-cabin telematics and automobile interconnect applications. The low-
power attributes inherent in antifuse technology make the eX devices ideal for designers who are looking
to integrate low-density, power-sensitive automotive applications into a programmable logic solution,
enabling quick time-to-market.
eX Family Architecture
The eX family is implemented on a high-voltage twin-well CMOS process using 0.22 µm design rules.
The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is
covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.
Interconnection among these logic modules is achieved using Microsemi’s patented metal-to-metal
programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of
amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25
Ω
with a capacitance of 1.0 fF for low-signal impedance. The antifuses are normally open circuit and, when
programmed, form a permanent low-impedance connection. The eX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines) control signals (Figure
1-1).
The R-cell registers feature programmable clock
polarity selectable on a register-by-register basis. This provides additional flexibility while allowing
mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from
either the hardwired clock or the routed clock.
The C-cell implements a range of combinatorial functions up to five inputs (Figure
1-2 on page 1-2).
Inclusion of the DB input and its associated inverter function enables the implementation of more than
4,000 combinatorial functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-flop to imitate an R-cell via the use of the CC
macro. This is particularly useful when implementing nontiming-critical paths and when the design
engineer is running out of R-cells. For more information about the CC macro, refer to the
Maximizing
Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros
application note.
S0
Routed
Data Input S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CKS
CKP
CLR
Figure 1-1 •
R-Cell
Revision 5
1 -1
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