NB6L11S
2.5 V 1:2 AnyLevel] Input
to LVDS Fanout Buffer /
Translator
The NB6L11S is a differential 1:2 clock or data receiver and will
accept AnyLevel™ input signals: LVPECL, CML, LVCMOS, LVTTL,
or LVDS. These signals will be translated to LVDS and two identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6L11S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6L11S has a wide input common mode range from
GND + 50 mV to V
CC
− 50 mV. Combined with the 50
W
internal
termination resistors at the inputs, the NB6L11S is ideal for translating
a variety of differential or single−ended Clock or Data signals to
350 mV typical LVDS output levels.
The NB6L11S is the 2.5 V version of the NB6N11S and is offered in
a small 3 mm X 3 mm 16−QFN package. Application notes, models,
and support documentation are available at
www.onsemi.com.
Features
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MARKING
DIAGRAM*
16
1
1
QFN−16
MN SUFFIX
CASE 485G
NB6L
11S
ALYW
G
G
•
•
•
•
•
•
•
•
Input Clock Frequency > 2.0 GHz
Input Data Rate > 2.5 Gb/s
RMS Clock Jitter −0.5 ps, Typical
622 Mb/s Data Dependent Jitter − 6 ps, Typical
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
Single Power Supply; V
CC
= 2.5 V
"
5%
These are Pb−Free Devices
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
V
TD
D
D
Q0
VOLTAGE (130 mV/div)
V
TD
Q1
Q1
Device DDJ = 10 ps
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2
23−1
(V
INPP
= 400 mV; Input Signal DDJ = 14 ps)
©
Semiconductor Components Industries, LLC, 2014
1
November, 2014 − Rev. 9
Publication Order Number:
NB6L11S/D
NB6L11S
Exposed Pad (EP)
V
CC
V
CC
V
CC
V
CC
16
Q0
Q0
Q1
Q1
15
14
13
1
2
NB6L11S
3
4
12 V
TD
11 D
10 D
9
V
TD
5
V
CC
6
NC
7
V
EE
8
V
EE
Figure 3. NB6L11S Pinout, 16−pin QFN
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EP
Name
Q0
Q0
Q1
Q1
V
CC
NC
V
EE
V
EE
V
TD
D
D
V
TD
V
CC
V
CC
V
CC
V
CC
−
LVPECL, CML, LVDS,
LVCMOS, LVTTL
LVPECL, CML, LVDS,
LVCMOS, LVTTL
−
−
−
−
−
I/O
LVDS Output
LVDS Output
LVDS Output
LVDS Output
−
Description
Non−inverted D output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Inverted D output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
Non−inverted D output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Inverted D output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
Positive Supply Voltage.
No Connect.
Negative Supply Voltage.
Negative Supply Voltage.
Internal 50
W
termination pin for D.
Inverted Differential Clock/Data Input (Note 1).
Non−inverted Differential Clock/Data Input (Note 1).
Internal 50
W
termination pin for D.
Positive Supply Voltage.
Positive Supply Voltage.
Positive Supply Voltage.
Positive Supply Voltage.
Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heat−sinking conduit. The exposed pad may only be
electrically connected to V
EE
.
1. In the differential configuration when the input termination pins (V
TD
, V
TD
) are connected to a common termination voltage or left open, and
if no signal is applied on D, D input, then the device will be susceptible to self−oscillation.
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2
NB6L11S
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
> 2 kV
> 200 V
> 1 kV
Pb−Free Pkg
QFN−16
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Level 1
UL 94 V−0 @ 0.125 in
225
Moisture Sensitivity (Note 2)
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
IN
I
IN
I
OSC
Parameter
Positive Power Supply
Positive Input
Input Current Through R
T
(50
W
Resistor)
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
1S2P (Note 3)
QFN−16
QFN−16
QFN−16
Condition 1
GND = 0 V
GND = 0 V
Static
Surge
Q or Q
Q to Q to GND
QFN−16
Continuous
Continuous
V
IN
≤
V
CC
Condition 2
Rating
3.8
3.8
35
70
12
24
−40 to +85
−65 to +150
41.6
35.2
4.0
265
°C
°C
°C/W
°C/W
°C/W
°C
Unit
V
V
mA
mA
mA
T
A
T
stg
q
JA
q
JC
T
sol
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB6L11S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS
V
CC
= 2.375 V to 2.625 V, GND = 0 V,
T
A
= −40°C to +85°C
Symbol
I
CC
Power Supply Current (Note 8)
Characteristic
Min
Typ
30
Max
45
Unit
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Figures 15, 16, 20, and 22)
V
th
V
IH
V
IL
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
GND +100
V
th
+ 100
GND
V
CC
− 100
V
CC
V
th
− 100
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 11, 12, 13, 14, 21, and 23)
V
IHD
V
ILD
V
CMR
V
ID
R
TIN
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage (V
IHD
− V
ILD
)
Internal Input Termination Resistor
100
GND
GND + 50
100
40
50
V
CC
V
CC
− 100
V
CC
− 50
V
CC
− GND
60
mV
mV
mV
mV
W
LVDS OUTPUTS
(Note 4)
V
OD
DV
OD
V
OS
DV
OS
V
OH
V
OL
Differential Output Voltage
Change in Magnitude of V
OD
for Complementary Output States (Note 9)
Offset Voltage (Figure 19)
Change in Magnitude of V
OS
for Complementary Output States (Note 9)
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 6)
900
250
0
1125
0
1
1425
1075
1
450
25
1375
25
1600
mV
mV
mV
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100
W
receiver termination resistor between differential pair. See Figure 18.
5. V
OH
max = V
OS
max +
½
V
OD
max.
6. V
OL
max = V
OS
min −
½
V
OD
max.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. Input termination pins open, D/D at the DC level within V
CMR
and output pins loaded with R
L
= 100
W
across differential.
9. Parameter guaranteed by design verification not tested in production.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NB6L11S
Table 5. AC CHARACTERISTICS
V
CC
= 2.375 V to 2.625 V, GND = 0 V; (Note 10)
−40°C
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPPmin
)
(Figure 4)
Maximum Operating Data Rate
Differential Input to Differential Output
Propagation Delay
Duty Cycle Skew (Note 11)
Within Device Skew (Note 16)
Device−to−Device Skew (Note 15)
f
in
= 1.0 GHz
f
in
= 1.5 GHz
Peak−to−Peak Data Dependent Jitter (Note 14)
f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
Output Rise/Fall Times @ 250 MHz
(20% − 80%)
Q, Q
100
70
120
RMS Random Clock Jitter (Note 13)
f
in
≤
1.0 GHz
f
in
= 1.5 GHz
f
in
= 2.0 GHz
Min
220
200
170
1.5
250
8
5
30
0.5
0.5
6
7
10
V
CC
−
GND
170
100
70
120
Typ
350
300
270
2.5
450
45
25
100
Max
Min
220
200
170
1.5
250
25°C
Typ
350
300
270
2.5
380
8
5
30
0.5
0.5
6
7
10
V
CC
−
GND
170
100
70
120
450
45
25
100
Max
Min
220
200
170
1.5
250
8
5
30
0.5
0.5
6
7
10
V
CC
−
GND
170
mV
ps
85°C
Typ
350
300
270
2.5
450
45
25
100
Max
Unit
mV
f
DATA
t
PLH
,
t
PHL
t
SKEW
Gb/s
ps
ps
t
JITTER
ps
V
INPP
t
r
t
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing V
INPPmin
with 50% duty cycle clock source and V
CC
− 1400 mV offset. All loading with an external R
L
= 100
W
across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 17 differential measurement of t
skew
= |t
PLH
− t
PHL
| for a nominal 50% differential clock input waveform @ 250 MHz.
12. Input voltage swing is a single−ended measurement operating in differential mode.
13. RMS jitter with 50% Duty Cycle input clock signal.
14. Deterministic jitter with input NRZ data at PRBS 2
23
−1 and K28.5.
15. Skew is measured between outputs under identical transition @ 250 MHz.
16. The worst case condition between Q0/Q0 and Q1/Q1 from D, D, when both outputs have the same transition.
400
OUTPUT VOLTAGE AMPLITUDE (mV)
350
300
250
200
150
100
50
0
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
85°C
25°C
−40°C
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 2.5 V)
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