LD39150
Ultra low drop BiCMOS voltage regulator
Datasheet
-
production data
Temperature range: -40 to 125 °C
Fast dynamic response to line and load
changes
Stable with ceramic capacitor
PPAK
DPAK
Available in PPAK, DPAK and DFN6 (3x3 mm)
Applications
Microprocessor power supply
DSPs power supply
DFN6 (3 x 3 mm)
Post regulators for switching suppliers
High efficiency linear regulator
Features
1.5 A guaranteed output current
Ultra low dropout voltage (200 mV typ. @ 1.5 A
load, 40 mV typ. @ 300 mA load)
Very low quiescent current (1 mA typ. @ 1.5 A
load, 1 µA max @ 25 °C in off mode)
Logic-controlled electronic shutdown
Current and thermal internal limit
Description
The LD39150 is a fast ultra low drop linear
regulator which operates from 2.5 V to 6 V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
1.5% output voltage tolerance @ 25 °C
Fixed and ADJ output voltages: 1.8 V, 2.5 V,
3.3 V, ADJ
Table 1. Device summary
Order codes
Output voltages
DPAK (tape and reel)
LD39150DT18-R
LD39150DT25-R
LD39150DT33-R
LD39150PT-R
LD39150PU-R
PPAK (tape and reel)
DFN
1.8 V
2.5 V
3.3 V
ADJ from 1.22 to 5.0 V
August 2017
This is information on a product in full production.
DocID13159 Rev 5
1/26
www.st.com
Contents
LD39150
Contents
1
2
3
4
5
6
7
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
7.2
7.3
7.4
7.5
External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1
8.2
8.3
PPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DFN6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1
9.2
DPAK and PPAK packaging information . . . . . . . . . . . . . . . . . . . . . . . . . 21
DFN6 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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DocID13159 Rev 5
LD39150
Diagram
1
Diagram
Figure 1. Block diagram
(*) Not present on ADJ versions.
DocID13159 Rev 5
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26
Pin configuration
LD39150
2
Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN)
6
5
4
TAB
1
2
3
CS26660
TAB
5
4
3
2
1
CS24140
3
TAB
2
1
CS24160
DFN6 (3 x 3 mm)
PPAK
DPAK
Table 2. Pin description
Pin n°
SYMBOL
DFN
PPAK DPAK
V
SENSE
/N.C.
ADJ
3
4
2
1
6
TAB
Exp.
Pad
TAB
2
4
1
3
2
1
3
V
I
V
O
V
INH
GND
N.C.
GND
For fixed versions: to be connected with LDO output voltage pins for DFN
package and not connected on PPAK
For adjustable version: Error amplifier input pin for V
O
from 1.22 to 5.0 V
LDO input voltage; V
I
from 2.5 V to 6 V, C
I
= 1 µF must be located at a
distance of not more than 0.5’’ from input pin.
LDO output voltage pins, with minimum C
O
= 2.2 µF needed for stability
(also refer to C
O
vs ESR stability chart)
Inhibit input voltage: ON MODE when V
INH
2 V, OFF MODE when V
INH
0.3 V (Do not leave floating, not internally pulled down/up)
Common ground
Not connected
Electrically connected to GND
Connect to GND (it is not a power GND)
NOTE
5
5
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DocID13159 Rev 5
LD39150
Typical application circuits
3
Typical application circuits
(C
I
and C
O
capacitors must be placed as close as possible to the IC pins)
Figure 3. LD39150 fixed version with inhibit
Note:
Inhibit pin is not internally pulled down/up then it must not be left floating. Disable the device
when connected to GND or to a positive voltage less than 0.3 V.
Figure 4. LD39150 adjustable version
V
O
= V
REF
(1 + R
1
/R
2
)
Note:
Set R2 as close as possible to 4.7 k
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