LPC111xLV/LPC11xxLVUK
32-bit ARM Cortex-M0 MCU; up to 32 kB flash, 8 kB SRAM;
8-bit ADC
Rev. 2 — 10 October 2012
Product data sheet
1. General description
The LPC111xLV/LPC11xxLVUK is an ARM Cortex-M0-based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC111xLV/LPC11xxLVUK operate at CPU frequencies of up to 50 MHz.
The peripherals of the LPC111xLV/LPC11xxLVUK include up to 32 kB of flash memory, up
to 8 kB of SRAM data memory, a Fast-mode Plus I
2
C-bus interface, one SSP/SPI
interface, one UART, four general-purpose counter/timers, an 8-bit ADC, and up to 27
general-purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug.
System tick timer.
Memory:
Up to 32 kB on-chip flash programming memory with a 256 byte page erase
function.
Up to 8 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Digital peripherals:
Up to 27 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors and a configurable open-drain mode.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current output driver on one pin.
High-current sink drivers on two I
2
C-bus pins in Fast-mode Plus.
Four general-purpose counter/timers with up to 7 capture inputs and 13 match
outputs.
Programmable windowed WDT.
Analog peripherals:
8-bit ADC with input multiplexing among up to 8 pins.
Serial interfaces:
NXP Semiconductors
LPC111xLV/LPC11xxLVUK
32-bit ARM Cortex-M0 microcontroller
UART with fractional baud rate generation and internal FIFO.
One SPI controller with SSP features and with FIFO and multi-protocol capabilities.
I
2
C-bus interface supporting full I
2
C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
12 MHz internal RC oscillator trimmed to 2.5 % accuracy for T
amb
= -20 °C to
+85 °C and to 5 % accuracy for T
amb
= -40 °C to -20 °C. The IRC can optionally be
used as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, and the Watchdog clock.
Power control:
Two reduced power modes: Sleep and Deep-sleep mode.
Ultra-low power consumption in Deep-sleep mode ( 1.6
A).
5
s
wake-up time from Deep-sleep mode.
Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
13 of the functional pins.
Power-On Reset (POR).
Brown-Out Detection (BOD) causing a forced reset.
Unique device serial number for identification.
Single power supply (1.65 V to 1.95 V)
Available as WLCSP25, HVQFN24, and HVQFN33 package. Other package options
are available for high-volume customers.
3. Applications
Mobile phones
Mobile accessories
Cameras
Tablets/Ultra books
Active cables
Portable medical electronics
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC1101LVUK
LPC1102LVUK
LPC1112LVFHN24/003
LPC1114LVFHN24/103
WLCSP25
WLCSP25
HVQFN24
HVQFN24
Description
wafer level chip-size package; 25 bumps; 2.17
2.32
0.56 mm
wafer level chip-size package; 25 bumps; 2.17
2.32
0.56 mm
plastic thermal enhanced very thin quad flat package; no leads; 24
terminals; body 4 x 4 x 0.85 mm
plastic thermal enhanced very thin quad flat package; no leads; 24
terminals; body 4 x 4 x 0.85 mm
All information provided in this document is subject to legal disclaimers.
Type number
Version
-
-
SOT616-3
SOT616-3
LPC111XLV_LPC11XXLVUK
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
2 of 53
NXP Semiconductors
LPC111xLV/LPC11xxLVUK
32-bit ARM Cortex-M0 microcontroller
Table 1.
Ordering information
…continued
Package
Name
Description
plastic thermal enhanced very thin quad flat package; no leads; 24
terminals; body 4 x 4 x 0.85 mm
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5
5
0.85 mm
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5
5
0.85 mm
Version
SOT616-3
n/a
n/a
HVQFN24
HVQFN33
HVQFN33
Type number
LPC1114LVFHN24/303
LPC1112LVFHI33/103
LPC1114LVFHI33/303
4.1 Ordering options
Table 2.
Ordering options
Flash Total
SPI/
in kB SRAM in SSP
kB
32
32
2
8
2
4
8
4
8
1
1
1
1
1
1
1
I2C UART ADC
GPI
O
pins
21
21
20
20
20
27
27
Package
Type number
LPC1101LVUK
LPC1102LVUK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6-channel
6-channel
6-channel
6-channel
6-channel
8-channel
8-channel
WLCSP25
WLCSP25
HVQFN24
HVQFN24
HVQFN24
HVQFN33
HVQFN33
LPC1112LVFHN24/003 16
LPC1114LVFHN24/103 32
LPC1114LVFHN24/303 32
LPC1112LVFHI33/103
LPC1114LVFHI33/303
16
32
LPC111XLV_LPC11XXLVUK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
3 of 53
NXP Semiconductors
LPC111xLV/LPC11xxLVUK
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
XTALIN
XTALOUT
RESET
SWD
LPC110xLVUK
LPC111xLV
TEST/DEBUG
INTERFACE
IRC
POR
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
controls
CLKOUT
ARM
CORTEX-M0
FLASH
16/32 kB
slave
HIGH-SPEED
GPIO
slave
AHB-LITE BUS
SRAM
2/4/8 kB
slave
slave
system bus
ROM
GPIO ports
slave
AHB TO APB
BRIDGE
RXD
TXD
DSR
(3)
, RTS,
CTS
(3)
, DTR
(3)
CT32B0_MAT[3:0]
CT32B0_CAP0
CT32B1_MAT[3:0]
CT32B1_CAP[1:0]
(1)
CT16B0_MAT[2:0]
CT16B0_CAP[1:0]
(1)
CT16B1_MAT[1:0]
(1)
CT16B1_CAP[1:0]
(1)
UART
10-bit/8-bit ADC
(2)
AD[7:0]
SCK0, SSEL0
MISO0, MOSI0
SPI0
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
I
2
C-BUS
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
WWDT
IOCON
SYSTEM CONTROL
SCL
SDA
002aag851
(1) CT16B1_MAT1, CT32B1_CAP1, CT1B0_CAP1, CT16B1_CAP1 available on HVQFN33 only. CT16B1_MAT0 available on
HVQFN33 and WLCSP25 packages only.
(2) 6 channels on WLCSP25 and HVQFN24 packages. 8 channels on HVQFN33 packages.
(3) DSR on WLCSP25 package only. DTR on HVQFN33 package only. CTS on HVQFN24 and HVQFN33 packages only.
Fig 1.
LPC111xLV/LPC11xxLVUK block diagram
LPC111XLV_LPC11XXLVUK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
4 of 53
NXP Semiconductors
LPC111xLV/LPC11xxLVUK
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
ball A1
index area
1
A
LPC1101/02LVUK
2
3
4
5
B
C
D
E
002aag852
Transparent top view
Fig 2.
Pin configuration WLCSP25 package
LPC111XLV_LPC11XXLVUK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 October 2012
5 of 53
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