STK11C68-M
STK11C68-M
CMOS nvSRAM
High Performance
8K x 8 Nonvolatile Static RAM
MIL-STD-883/SMD # 5962-92324
FEATURES
•
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•
•
•
•
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•
•
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35, 45 and 55ns Access Times
17, 20 and 25ns Output Enable Access
Unlimited Read and Write to
SRAM
Software
STORE
Initiation
Automatic
STORE
Timing
100,000
STORE
cycles to
EEPROM
10 year data retention in
EEPROM
Automatic
RECALL
on Power Up
Software
RECALL
Initiation
Unlimited
RECALL
cycles from
EEPROM
Single 5V
±
10% Operation
Available in multiple standard packages
DESCRIPTION
The Simtek STK11C68-M is a fast static
RAM
(35, 45
and 55ns), with a nonvolatile electrically-erasable
PROM
(
EEPROM
) element incorporated in each static memory
cell. The
SRAM
can be read and written an unlimited
number of times, while independent nonvolatile data
resides in
EEPROM
. Data transfers from the
SRAM
to
the
EEPROM
(
STORE
), or from the
EEPROM
to the
SRAM
(
RECALL
) are initiated through software se-
quences. It combines the high performance and ease
of use of a fast
SRAM
with nonvolatile data integrity.
The STK11C68-M is pin compatible with industry stan-
dard
SRAM
s and is available in a 28-pin 300 mil
ceramic DIP or 28-pad LCC package. Commercial and
industrial devices are also available.
LOGIC BLOCK DIAGRAM
EEPROM ARRAY
256 x 256
A
3
A
4
ROW DECODER
PIN CONFIGURATIONS
A
7
A
12
Vcc
NC
W
NC
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3
2
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
0
A
12
4
5
6
7
8
9
10
11
12
1
28 27
26
25
24
23
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
STORE
STATIC RAM
ARRAY
256 x 256
RECALL
A
5
A
6
A
7
A
8
A
9
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
TOP VIEW
22
21
20
19
18
DQ
0
DQ
1
13 14 15 16 17
DQ
2
Vss
DQ
3
DQ
4
STORE/
RECALL
CONTROL
28 - LCC
DQ
5
28 - 300 C-DIP
COLUMN I/O
INPUT BUFFERS
PIN NAMES
A
0
- A
12
W
DQ
0
- DQ
7
E
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+5V)
Ground
COLUMN DECODER
A
0
A
1
A
2
A
10
A
11
G
G
V
CC
V
SS
E
W
4-31
STK11C68-M
ABSOLUTE MAXIMUM RATINGS
a
Voltage on typical input relative to V
SS
. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ
0-7
and G. . . . . . . . . . . . . . . . . . .–0.5V to (V
CC
+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
(One output at a time, one second duration)
Note a:
Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
I
CC b
1
(V
CC
= 5.0V
±
10%)
MIN
MAX
90
85
80
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
0.4
–55
125
V
°C
t
AVAV
= 35ns
t
AVAV
= 45ns
t
AVAV
= 55ns
E
≥
(V
CC
– 0.2V)
all others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
27
23
20
t
AVAV
= 35ns
t
AVAV
= 45ns
t
AVAV
= 55ns
E
≥
V
IH
; all others cycling
E
≥
(V
CC
– 0.2V)
all others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
±1
±5
2.2
V
SS
–.5
2.4
V
CC
+.5
0.8
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
All Inputs
All Inputs
I
OUT
= –4mA
I
OUT
= 8mA
NOTES
PARAMETER
Average V
CC
Current
I
CC d
2
Average V
CC
Current
during STORE cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
50
I
SB c
1
I
SB
c
2
Average V
CC
Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current (Any Input)
Off State Output Leakage Current
Input Logic "1" Voltage
Input Logic "0" Voltage
Output Logic "1" Voltage
Output Logic "0" Voltage
Operating Temperature
2
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC 1
is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: I
CC2
is the average current required for the duration of the store cycle (t
STORE
) after the sequence (t
WC
) that initiates the cycle.
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . .
≤
5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Output
5.0V
480 Ohms
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
(T
A
=25°C, f=1.0MHz)
MAX
5
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
255 Ohms
PARAMETER
Input Capacitance
Output Capacitance
30pF
INCLUDING
SCOPE
AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
4-32
STK11C68-M
READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
11A
#1, #2
t
ELQV
t
AVAVg
t
AVQVh
t
GLQV
t
AXQX
t
ELQX
t
EHQZi
t
GLQX
t
GHQZi
t
ELICCHe
t
EHICCLc,e
t
WHQV
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
t
WR
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Write Recovery Time
0
35
45
0
17
0
45
55
5
5
17
0
20
0
55
65
35
35
20
5
5
20
0
25
STK11C68-35M
MIN
MAX
35
45
45
25
5
5
25
STK11C68-45M
MIN
MAX
45
55
55
25
(V
CC
= 5.0V
±
10%)
STK11C68-55M
MIN
MAX
55
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note g: For READ CYCLE #1 and #2, W must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured
±
200mV from steady state output voltage.
READ CYCLE #1
g,h
2
t
AVAV
ADDRESS
5
3
t
AVQV
DATA VALID
t
AXQX
DQ (Data Out)
W
11A
t
WHQV
READ CYCLE #2
g
2
t
AVAV
ADDRESS
1
t
ELQV
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
DATA VALID
E
t
ELQX
4
6
G
t
GLQV
8
t
GLQX
DQ (Data Out)
10
t
ELICCH
I
CC
ACTIVE
STANDBY
W
11A
t
WHQV
4-33
STK11C68-M
WRITE CYCLES #1 & #2; G high
SYMBOLS
NO.
12
13
14
15
16
17
18
19
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
PARAMETER
STK11C68-35M
MIN
35
30
30
18
0
30
0
0
MAX
STK11C68-45M
MIN
45
35
35
20
0
35
0
0
MAX
(V
CC
= 5.0V
±
10%)
STK11C68-55M
MIN
55
45
45
30
0
45
0
0
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLES #1 & #2; G low
SYMBOLS
NO.
12
13
14
15
16
17
18
19
20
21
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ i,m
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
5
PARAMETER
STK11C68-35M
MIN
45
35
35
30
0
35
0
0
35
5
MAX
STK11C68-45M
MIN
45
35
35
30
0
35
0
0
35
MAX
(V
CC
= 5.0V
±
10%)
STK11C68-55M
MIN
55
45
45
30
0
45
0
0
35
5
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note i:
Note k:
Note m:
Measured + 200mV from steady state output voltage.
E or W must be
≥
V
IH
during address transitions.
If W is low when E goes low, the outputs remain in the high impedance state.
4-34
STK11C68-M
WRITE CYCLE #1:
W CONTROLLED
k
12
t
AVAV
ADDRESS
14
t
ELWH
E
18
17
t
AVWH
19
t
WHAX
t
AVWL
W
13
t
WLWH
15
t
DVWH
16
t
WHDX
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
DATA VALID
21
t
WHQX
HIGH IMPEDANCE
WRITE CYCLE #2:
E CONTROLLED
k
12
t
AVAV
ADDRESS
18
t
AVEL
E
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
DATA IN
DATA VALID
14
t
ELEH
19
t
EHAX
16
t
EHDX
DATA OUT
HIGH IMPEDANCE
4-35
Test/Measurement
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