PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
Rev. 5 — 24 April 2014
Product data sheet
1. General description
The PCA9541A is a 2-to-1 I
2
C-bus master selector designed for high reliability dual
master I
2
C-bus applications where system operation is required, even when one master
fails or the controller card is removed for maintenance. The two masters (for example,
primary and back-up) are located on separate I
2
C-buses that connect to the same
downstream I
2
C-bus slave devices. I
2
C-bus commands are sent by either I
2
C-bus master
and are used to select one master at a time. Either master at any time can gain control of
the slave devices if the other master is disabled or removed from the system. The failed
master is isolated from the system and does not affect communication between the
on-line master and the slave devices on the downstream I
2
C-bus.
Two versions are offered for different architectures. PCA9541A/01 with channel 0
selected at start-up, and PCA9541A/03 with no channel selected after start-up.
The interrupt outputs are used to provide an indication of which master has control of the
bus. One interrupt input (INT_IN) collects downstream information and propagates it to
the 2 upstream I
2
C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let
the previous bus master know that it is not in control of the bus anymore and to indicate
the completion of the bus recovery/initialization sequence. If the masking option is set,
those interrupts can be disabled and do not generate an interrupt.
A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a
STOP condition in order to set the downstream I
2
C-bus devices to an initialized state
before actually switching the channel to the selected master.
An interrupt is sent to the upstream channel when the recovery/initialization procedure is
completed.
An internal bus sensor senses the downstream I
2
C-bus traffic and generates an interrupt
if a channel switch occurs during a non-idle bus condition. This function is enabled when
the PCA9541A recovery/initialization is not used. The interrupt signal informs the master
that an external I
2
C-bus recovery/initialization must be performed. It can be disabled and
an interrupt is not generated.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit
the maximum high voltage, which will be passed by the PCA9541A. This allows the use of
different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate
with 5 V devices without any additional protection.
The PCA9541A does not isolate the capacitive loading on either side of the device, so the
designer must take into account all trace and device capacitances on both sides of the
device, and pull-up resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O
pins are 6.0 V tolerant.
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin
LOW resets the I
2
C-bus state machine and configures the device to its default state as
does the internal Power-On Reset (POR) function.
2. Features and benefits
2-to-1 bidirectional master selector
I
2
C-bus interface logic; compatible with SMBus standards
PCA9541A/01 powers up with Channel 0 selected
PCA9541A/03 powers up with no channel selected and either master can take control
of the bus
Active LOW interrupt input
2 active LOW interrupt outputs
Active LOW reset input
4 address pins allowing up to 16 devices on the I
2
C-bus
Channel selection via I
2
C-bus
Bus initialization/recovery function
Bus traffic sensor
Low R
on
switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Software identical for both masters
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
6.0 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO16, TSSOP16, HVQFN16
3. Applications
High reliability systems with dual masters
Gatekeeper multiplexer on long single bus
Bus initialization/recovery for slave devices without hardware reset
Allows masters without arbitration logic to share resources
PCA9541A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 24 April 2014
2 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
4. Ordering information
Table 1.
Ordering information
Topside
marking
PCA9541AD/1
PCA9541AD/3
Package
Name
SO16
SO16
TSSOP16
TSSOP16
HVQFN16
HVQFN16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4
4
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4
4
0.85 mm
Version
SOT109-1
SOT109-1
SOT403-1
SOT403-1
SOT629-1
SOT629-1
Type number
PCA9541AD/01
PCA9541AD/03
PCA9541APW/01 9541A/1
PCA9541APW/03 9541A/3
PCA9541ABS/01
PCA9541ABS/03
41A1
41A3
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PCA9541AD/01,112
PCA9541AD/01,118
PCA9541AD/03
PCA9541AD/03,112
PCA9541AD/03,118
PCA9541APW/01
PCA9541APW/01,112
PCA9541APW/01,118
PCA9541APW/03
PCA9541APW/03,112
PCA9541APW/03,118
PCA9541ABS/01
PCA9541ABS/03
PCA9541ABS/01,118
PCA9541ABS/03,118
Package
Packing method
Minimum Temperature
order
quantity
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
PCA9541AD/01
SO16
SO16
SO16
SO16
TSSOP16
TSSOP16
TSSOP16
TSSOP16
HVQFN16
HVQFN16
Standard marking
1000
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
2500
Standard marking
1000
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
2500
Standard marking
2400
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
2500
Standard marking
2400
* IC’s tube - DSC bulk pack
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
2500
6000
6000
PCA9541A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 24 April 2014
3 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
5. Block diagram
PCA9541A
SCL_MST0
SDA_MST0
INPUT
FILTER
STOP
DETECTION
BUS
SENSOR
A3
A2
A1
A0
RESET
V
DD
POWER-ON
RESET
I
2
C-BUS
CONTROL
AND
REGISTER
BANK
SLAVE
CHANNEL
SWITCH
CONTROL
LOGIC
SCL_SLAVE
SDA_SLAVE
SCL_MST1
SDA_MST1
INPUT
FILTER
STOP
DETECTION
BUS
RECOVERY/
INITIALIZATION
OSCILLATOR
INT0
INT1
INTERRUPT
LOGIC
INT_IN
002aae656
V
SS
Fig 1.
Block diagram of PCA9541A
PCA9541A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 24 April 2014
4 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
6. Pinning information
6.1 Pinning
PCA9541AD/01
PCA9541AD/03
INT0
SDA_MST0
SCL_MST0
RESET
SCL_MST1
SDA_MST1
INT1
V
SS
1
2
3
4
5
6
7
8
002aae657
16 V
DD
15 INT_IN
14 SDA_SLAVE
13 SCL_SLAVE
12 A3
11 A2
10 A1
9
A0
INT0
SDA_MST0
SCL_MST0
RESET
SCL_MST1
SDA_MST1
INT1
V
SS
1
2
3
4
5
6
7
8
002aae658
16 V
DD
15 INT_IN
14 SDA_SLAVE
13 SCL_SLAVE
12 A3
11 A2
10 A1
9
A0
PCA9541APW/01
PCA9541APW/03
Fig 2.
Pin configuration for SO16
16 SDA_MST0
Fig 3.
Pin configuration for TSSOP16
terminal 1
index area
SCL_MST0
RESET
SCL_MST1
SDA_MST1
1
2
3
4
5
6
7
8
13 INT_IN
12 SDA_SLAVE
11 SCL_SLAVE
10 A3
9
A2
A1
15 INT0
V
SS
PCA9541ABS/01
PCA9541ABS/03
INT1
A0
14 V
DD
002aae659
Transparent top view
Fig 4.
Pin configuration for HVQFN16
PCA9541A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 24 April 2014
5 of 45
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