Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Range
at Ta = -40°C to +85°C, VSS = 0V
Parameter
Supply voltage
Symbol
VDD
VLCD
VDD
VLCD
When the display contrast adjustment circuit is used.
VLCD
When the display contrast adjustment circuit is not
used.
Output voltage
Input voltage
VLCD0
VLCD1
VLCD0
VLCD1
VLCD4
+4.5
3/4
(VLCD0-
VLCD4)
VLCD2
VLCD2
2/4
(VLCD0-
VLCD4)
VLCD3
VLCD3
1/4
(VLCD0-
VLCD4)
VLCD4
VLCD4
0
VLCD0
1.5
VLCD0
V
VLCD0
VLCD
V
Conditions
min
2.7
7.0
Ratings
typ
max
3.6
10.0
V
4.5
10.0
unit
Continued on next page.
No.A1417-2/54
LC75812PT
Continued from preceding page.
Parameter
Input high level voltage
Symbol
VIH1
CE, CL, DI, INH
CE, CL, DI, INH
VIH2
VIH3
Input low level voltage
VIL1
VIL2
Output pull-up voltage
Recommended external
resistor for RC oscillation
Recommended external
capacitor for RC oscillation
Guaranteed range of RC
oscillation
External clock operating frequency
External clock duty cycle
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
DO output delay time
DO rise time
fCK
DCK
tds
tdh
tcp
tcs
tch
tφH
tφL
tdc
tdr
OSC external clock operating mode
OSC external clock operating mode
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
CL
DO RPU=4.7kΩ CL=10pF *1
DO RPU=4.7kΩ CL=10pF *1
[Figure 4]
[Figure 4]
fosc
OSC RC oscillator operating mode
150
100
30
160
160
160
160
160
160
160
1.5
1.5
Cosc
OSC RC oscillator operating mode
VOUP
Rosc
VDD=2.7 to 3.6V
OSC external clock operating mode
KI1 to KI5
CE, CL, DI, INH, KI1 to KI5
OSC external clock operating mode
DO
OSC RC oscillator operating mode
Conditions
min
0.8VDD
0.8VDD
0.8VDD
0.6VDD
0
0
0
10
470
300
300
50
600
600
70
Ratings
typ
max
3.6
5.5
VDD
VDD
0.2VDD
0.2VDD
5.5
V
kΩ
pF
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
μs
μs
V
unit
V
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
[Figure 2],[Figure 3]
Note:
*1.
Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and
the load capacitance CL.
Electrical Characteristics
for the Allowable Operating Ranges
Parameter
Hysteresis
Power-down detection
voltage
Input high level current
IIH1
CE, CL, DI, INH
VI=3.6V
VI=5.5V
VDD=2.7 to 3.6V
IIH2
Input low level current
IIL1
IIL2
Input floating voltage
Pull-down resistance
Output off leakage current
Output high level voltage
VIF
RPD
IOFFH
VOH1
VOH2
VOH3
VOH4
Output low level voltage
VOL1
VOL2
VOL3
VOL4
VOL5
OSC
CE, CL, DI, INH
OSC
KI1 to KI5
KI1 to KI5
DO
S1 to S65
COM1 to COM9
KS1 to KS7
P1 to P3
S1 to S65
COM1 to COM9
KS1 to KS7
P1 to P3
DO
VDD=3.3V
VO=5.5V
IO=-20μA
IO=-100μA
IO=-250μA
IO=-1mA
IO=20μA
IO=100μA
IO=12.5μA
IO=1mA
IO=1mA
0.1
0.1
0.4
VLCD0-0.6
VLCD0-0.6
VDD-0.8
VDD-0.9
VLCD4+0.6
VLCD4+0.6
1.2
0.9
0.3
V
VDD-0.4
VDD-0.1
V
50
100
VI=VDD external clock operating mode
VI=0V
VI=0V external clock operating mode
-5.0
-5.0
0.05VDD
250
6.0
Symbol
VH
VDET
Pins
CE, CL, DI, INH,
KI1 to KI5
2.0
Conditions
min
Ratings
typ
0.1VDD
2.2
2.4
5.0
5.0
5.0
μA
V
kΩ
μA
μA
max
V
V
unit
Continued on next page.
No.A1417-3/54
LC75812PT
Continued from preceding page.
Parameter
Output middle level
voltage *2
Symbol
VMID1
Pins
S1 to S65
IO=±20μA
Conditions
min
2/4
(VLCD0
-VLCD4)
-0.6
VMID2
COM1 to COM9
IO=±100μA
3/4
(VLCD0
-VLCD4)
-0.6
VMID3
COM1 to COM9
IO=±100μA
1/4
(VLCD0
-VLCD4)
-0.6
Oscillator frequency
Current drain
fosc
IDD1
IDD2
ILCD1
ILCD2
OSC
VDD
VDD
VLCD
VLCD
Rosc=10kΩ, Cosc=470pF
sleep mode
VDD=3.6V, output open,
fosc=300kHz
sleep mode
VLCD=10.0V, output open,
fosc=300kHz, When the display
contrast adjustment circuit is used.
ILCD3
VLCD
VLCD=10.0V, output open,
fosc=300kHz, When the display
contrast adjustment circuit is not
used.
450
500
210
300
Ratings
typ
max
2/4
(VLCD0
-VLCD4)
+0.6
3/4
(VLCD0
-VLCD4)
+0.6
1/4
(VLCD0
-VLCD4)
+0.6
390
100
1000
15
900
μA
kHz
V
unit
200
400
Note:
*2.
Excluding the bias voltage generation divider resistor built into the VLCD0, VLCD1, VLCD2, VLCD3,
and VLCD4. (See Figure 1.)
VLCD
CONTRAST
ADJUSTER
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
Excluding these resistors
To the common and segment drivers
[Figure 1]
No.A1417-4/54
LC75812PT
(1) When CL is stopped at the low level
CE
tφH
tφL
VIH1
≈
VIL1
≈ ≈ ≈ ≈ ≈
VIH1
CL 50%
VIL1
DI VIH1
VIL1
tds
DO
≈ ≈
≈ ≈
tcp
tcs
tch
tdh
D0
tdc
tdr
D1
(2) When CL is stopped at the high level
≈
[Figure 2]
VIH1
tφL
CL
tφH
VIH1
50%
VIL1
VIH1
≈
≈
CE
VIL1
≈ ≈ ≈ ≈ ≈
≈
DI
tds
DO
tdh
VIL1
D0
D1
tdc
≈ ≈ ≈ ≈
tcp
tcs
tch
tdr
[Figure 3]
(3) OSC pin clock timing in external clock operating mode
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