CY62167EV30 MoBL
®
16-Mbit (1M × 16/2M × 8) Static RAM
16-Mbit (1M × 16/2M × 8) Static RAM
Features
■
■
■
TSOP I package configurable as 1M × 16 or 2M × 8 SRAM
Very high speed: 45 ns
Temperature ranges
❐
Industrial: –40 °C to +85 °C
❐
Automotive-A: –40 °C to +85 °C
Wide voltage range: 2.20 V to 3.60 V
Ultra-low standby power
❐
Typical standby current: 1.5
A
❐
Maximum standby current: 12
A
Ultra-low active power
❐
Typical active current: 2.2 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE Features
Automatic power-down when deselected
CMOS for optimum speed and power
Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages
■
■
low active current. Ultra low active current is ideal for providing
More Battery Life (MoBL
®
) in portable applications such as
cellular telephones. The device also has an automatic power
down feature that reduces power consumption by 99 percent
when addresses are not toggling. Place the device into standby
mode when deselected (CE
1
HIGH or CE
2
LOW or both BHE and
BLE are HIGH). The input and output pins (I/O
0
through I/O
15
)
are placed in a high impedance state when: the device is
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH), or a write operation is in progress (CE
1
LOW,
CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
19
). If Byte High Enable (BHE) is LOW, then data from the I/O
pins (I/O
8
through I/O
15
) is written into the location specified on
the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See
Truth Table on page 12
for a complete description of read and write modes.
For a complete list of related documentation,
click here.
■
■
■
■
■
Functional Description
The CY62167EV30 is a high performance CMOS static RAM
organized as 1M words by 16 bits or 2M words by 8 bits. This
device features an advanced circuit design that provides an ultra
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
1M × 16 / 2M x 8
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BYTE
BHE
WE
OE
BLE
CE
2
Power Down
Circuit
CE
1
BHE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
CE
2
CE
1
Cypress Semiconductor Corporation
Document Number: 38-05446 Rev. *P
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 11, 2017
CY62167EV30 MoBL
®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-05446 Rev. *P
Page 2 of 19
CY62167EV30 MoBL
®
Pin Configuration
Figure 1. 48-ball VFBGA pinout (Top View)
[1, 2]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
A
18
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
A
19
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
V
CC
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Figure 2. 48-pin TSOP I pinout (Top View)
[2, 3]
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE
2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE
1
A0
Product Portfolio
Power Dissipation
Product
Range
V
CC
Range (V)
Min
CY62167EV30LL
Industrial/Automotive-A
2.2
Typ
[4]
3.0
Max
3.6
45
Speed
(ns)
Operating I
CC
(mA)
f = 1 MHz
Typ
[4]
2.2
Max
4.0
f = f
max
Typ
[4]
25
Max
30
Standby I
SB2
(A)
Typ
[4]
1.5
Max
12
Notes
1. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.
2. NC pins are not connected on the die.
3. The BYTE pin in the 48-pin TSOP I package has to be tied to V
CC
to use the device as a 1 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2 M × 8
SRAM by tying the BYTE signal to V
SS
. In the 2 M × 8 configuration, Pin 45 is A20, while BHE, BLE and I/O
8
to I/O
14
pins are not used.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document Number: 38-05446 Rev. *P
Page 3 of 19
CY62167EV30 MoBL
®
DC input voltage
[5, 6]
....... –0.3 V to 3.9 V (V
CC(max)
+ 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >200 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential
[5, 6]
.... –0.3 V to 3.9 V (V
CC(max)
+ 0.3 V)
DC voltage applied to outputs
in High Z state
[5, 6]
........... –0.3 V to 3.9 V (V
CC(max)
+ 0.3 V)
Operating Range
Device
CY62167EV30LL
Range
Industrial/
Automotive-A
Ambient
Temperature
–40 °C to +85 °C
V
CC
[7]
2.2 V to
3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
I
IX
I
OZ
I
CC
I
SB1[10]
Input leakage current
Output leakage current
V
CC
operating supply current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output disabled
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
Test Conditions
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1 mA
45 ns (Industrial/
Automotive-A)
Min Typ
2.0
2.4
–
–
1.8
2.2
–0.3
For VFBGA package –0.3
For TSOP I package –0.3
–1
–1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
25
2.2
1.5
[8]
Unit
V
V
V
V
V
V
V
V
V
A
A
mA
mA
A
Max
–
–
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
0.7
[9]
+1
+1
30
4.0
12
Automatic power down current – CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V
CMOS inputs
or (BHE and BLE) > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V,
f = f
max
(address and data only),
f = 0 (OE, and WE), V
CC
= V
CC(max)
I
SB2
[10]
Automatic power down current – CE
1
> V
CC
– 0.2 V or
CMOS inputs
CE
2
< 0.2 V or
V
CC
= V
CC(max)
Temperature = 25 °C
–
–
–
1.5
–
–
3.0
[11]
3.5
[11]
12
A
V
CC
= 3.0 V,
(BHE and BLE) > V
CC
– 0.2 V, Temperature = 40 °C
V
IN
> V
CC
– 0.2 V or
V
CC
= V
CC(max)
V
IN
< 0.2 V, f = 0
Temperature = 85 °C
Notes
5. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
7. Full Device AC operation assumes a 100
s
ramp time from 0 to V
CC(min)
and 200
s
wait time after V
CC
stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
9. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V. This is
applicable to TSOP I package only.
10. Chip enables (CE
1
and CE
2
), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the I
SB1
/I
SB2
/ I
CCDR
spec. Other inputs can be left floating
11. This parameter is guaranteed by design.
Document Number: 38-05446 Rev. *P
Page 4 of 19
CY62167EV30 MoBL
®
Capacitance
Parameter
[12]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter
[12]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
48-ball VFBGA 48-pin TSOP I Unit
55
16
60
4.3
°C/W
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
GND
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
R1
R2
R
TH
V
TH
2.2 V to 2.7 V
16667
15385
8000
1.20
2.7 V to 3.6 V
1103
1554
645
1.75
Unit
V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05446 Rev. *P
Page 5 of 19
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