DATASHEET
ISL78322
Dual 2A/1.7A, 2.25MHz High-Efficiency, Synchronous Buck Regulator
The
ISL78322
is a high-efficiency, dual synchronous step-down
DC/DC regulator that can deliver up to 2A/1.7A continuous
output current per channel. The channels are 180° out-of-
phase for input RMS current and EMI reduction. The supply
voltage range of 2.8V to 5.5V allows for the use of a single Li+
cell, three NiMH cells or a regulated 5V input. The current
mode control architecture enables very low duty cycle
operation at high frequency with fast transient response and
excellent loop stability. The ISL78322 operates at 2.25MHz
switching frequency, which allows for the use of small, low cost
inductors and capacitors. Each channel is optimized for
generating an output voltage as low as 0.6V.
The ISL78322 has a forced PWM mode that reduces noise and
RF interference.
The ISL78322 offers a 1ms Power-Good (PG) signal to monitor
both outputs at power-up. When shut down, ISL78322
discharges the output capacitors. Other features include
internal digital soft-start, enable for power sequence,
overcurrent protection, and thermal shutdown. The ISL78322
is offered in a 4mmx3mm, 12 Lead DFN package with 1mm
maximum height. The complete converter occupies less than
1.8cm
2
area.
The ISL78322 is qualified to AEC-Q100 and specified for
operation across the -40°C to +105°C (grade 2) ambient
temperature range.
FN7908
Rev 3.00
November 30, 2016
Features
• Dual 2A/1.7A high-efficiency, synchronous buck regulator
with up to 97% efficiency
• 2.8V to 5.5V input supply range
• 180
°
out-of-phase outputs reduce ripple current and EMI
• Start-up with prebiased output prevents negative current
flow in output stage
• External synchronization up to 8MHz
• Negative current detection and protection
• 100% maximum duty cycle for lowest dropout
• Internal current mode compensation
• Peak current limiting, hiccup mode short-circuit protection,
and over-temperature protection
• Pb-free (RoHs compliant)
•
AEC-Q100
qualified component
Applications
• DC/DC POL modules
• µC/µP, FPGA, and DSP power
• Automotive embedded processor power supply systems
Related Literature
• For a full list of related documents, visit our website
-
ISL78322
product page
100
90
80
3.3V
OUT2
PWM
70
60
50
2.25MHz 5V
IN
AT +25°C
40
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
EFFICIENCY (%)
2.5V
OUT1
PWM
OUTPUT LOAD (A)
FIGURE 1. CHARACTERISTIC CURVE
FN7908 Rev 3.00
November 30, 2016
Page 1 of 17
ISL78322
Typical Applications
L
1
1.2µH
LX1
C
2
22µF
PGND
INPUT 2.8V TO 5.5V
VIN
EN1
ISL78322
EN2
LX2
PG
PGND
SYNC
FB2
R
6
100k
C
4
22µF
R
5
200k
C
5
10pF
L
2
1.2µH
R
2
316k
FB1
R
3
100k
C
3
10pF
OUTPUT1
2.5V/2A
C
1
2 x 10µF
OUTPUT2
1.8V/1.7A
FIGURE 2. TYPICAL APPLICATION DIAGRAM - DUAL INDEPENDENT OUTPUTS
Ordering Information
PART NUMBER (Notes
1, 2, 3)
ISL78322ARZ
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see device information page for
ISL78322.
For more information on MSL, see techbrief
TB363.
PART MARKING
BEKA
TEMP. RANGE (°C)
-40 to +105
PACKAGE
(RoHS COMPLIANT)
12 Ld 4x3 DFN
PKG.
DWG. #
L12.4x3
TABLE 1. COMPONENT VALUE SELECTION
V
OUT
C
1
C
2
(or C
4
)
C
3
(or C
5
)
L
1
(or L
2
)
R
2
(or R
5
)
R
3
(or R
6
)
0.8V
2x10µF
22µF
10pF
1.0~2.2µH
33k
100k
1.2V
2x10µF
22µF
10pF
1.0~2.2µH
100k
100k
1.5V
2x10µF
22µF
10pF
1.0~2.2µH
150k
100k
1.8V
2x10µF
22µF
10pF
1.5~3.3µH
200k
100k
2.5V
2x10µF
22µF
10pF
1.5~3.3µH
316k
100k
3.3V
2x10µF
22µF
10pF
1.5~4.7µH
450k
100k
In
Table 1,
the minimum output capacitor value is given for
different output voltages to make sure the whole converter
system is stable. Output capacitance should increase to support
faster load transient requirement.
FN7908 Rev 3.00
November 30, 2016
Page 2 of 17
ISL78322
Block Diagram
SHUTDOWN
EN1
SOFT-
Soft
START
Start
27pF
250k
PWM
LOGIC
CONTROLLER
PROTECTION
DRIVER
VCC SHUTDOWN
VIN1
3pF
SLOPE
COMP
FB1
1.6k
0.2V
SCP
+
+
OCP
+
+
CSA1
VIN
0.546V
1M
PG
SHUTDOWN
EN2
SOFT-
Soft
START
Start
3pF
SLOPE
COMP
FB2
1.6k
0.2V
SCP
+
+
OCP
+
0.546V
NEGATIVE
CURRENT LIMIT
ZERO- CROSS
SENSING
FN7908 Rev 3.00
November 30, 2016
+
BANDGAP 0.6V
+
+
+
BANDGAP 0.6V
EAMP
+
COMP
LX1
PGND
1.25V
OSCILLATOR
NEGATIVE
CURRENT LIMIT
1ms
DELAY
ZERO - CROSS
SENSING
SYNC
THERMAL
SHUT DOWN
27pF
250k
SHUTDOWN
VCC
SHUTDOWN
VIN2
EAMP
+
COMP
PWM
LOGIC
CONTROLLER
PROTECTION
DRIVER
LX2
PGND
+
CSA2
1.1V
FIGURE 3. BLOCK DIAGRAM
Page 3 of 17
ISL78322
Pin Configuration
ISL78322
(12 LD DFN)
TOP VIEW
FB1
EN1
PG
VIN1
LX1
PGND1
1
2
3
4
5
6
PAD
12 FB2
11 EN2
10 SYNC
9
8
7
VIN2
LX2
PGND2
Pin Description
PIN
NUMBER
1
SYMBOL
FB1
DESCRIPTION
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to
any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to
meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the
Channel 1 regulator output voltage.
Regulator Channel 1 enable pin. Enable the output, V
OUT1
, when driven to high. Shutdown the V
OUT1
and discharge output
capacitor when driven to low. Do not leave this pin floating.
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed power-good signal for both the V
OUT1
and V
OUT2
voltages.
There is an internal 1MΩ pull-up resistor.
Input supply voltage for Channel 1. Connect 10µF ceramic capacitor to PGND1.
Switching node connection for Channel 1. Connect to one terminal of inductor for V
OUT1
.
Negative supply for Power Stage 1.
Negative supply for Power Stage 2 and system ground.
Switching node connection for Channel 2. Connect to one terminal of inductor for V
OUT2
.
Input supply voltage for Channel 2 and to provide logic bias. Make sure that VIN2 is
≥
VIN1. Connect 10µF ceramic capacitor to
PGND2.
Connect to logic low or ground for forced PWM mode. Connect to an external function generator for synchronization. Negative edge
trigger. Do not leave this pin floating.
Regulator Channel 2 enable pin. Enable the output, V
OUT2
, when driven to high. Shutdown the V
OUT2
and discharge output
capacitor when driven to low. Do not leave this pin floating.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to
any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to
meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the
Channel 2 regulator output voltage.
2
3
4
5
6
7
8
9
10
11
12
EN1
PG
VIN1
LX1
PGND1
PGND2
LX2
VIN2
SYNC
EN2
FB2
-
EXPOSED The exposed pad must be connected to the PGND1 and PGND2 pins for proper electrical performance. Add as many vias as
PAD
possible for optimal thermal performance.
FN7908 Rev 3.00
November 30, 2016
Page 4 of 17
ISL78322
Absolute Maximum Ratings
(Reference to GND)
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
4x3 DFN Package (Notes
4, 5)
. . . . . . . .
41
3
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
EN1, EN2, PG, SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to V
IN
+ 0.3V
LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 7V (20ms)
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Machine Model(Tested per JESD22-C101E) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per AEC-Q100-11) . . . . . . . . . . . . . . . 2kV
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
V
IN
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 5.5V
Load Current Range Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A
Load Current Range Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.7A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5.
JC
, “case temperature” location is at the center of the exposed metal pad on the package underside.
Unless otherwise noted, all parameter limits are established over the recommended operating conditions:
TA = -40°C to +105°C, VIN = 2.8V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 1.2µH, C1 = 2 x 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A.
(Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply across the operating temperature range, -40°C to +105°C.
PARAMETER
INPUT SUPPLY
V
IN
Undervoltage Lock-out Threshold
V
UVLO
Rising
Falling
Quiescent Supply Current
Shutdown Supply Current
OUTPUT REGULATION
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
Output Voltage Accuracy
V
FB_
I
FB_
V
FB
= 0.55V
SYNC = V
IN
, Io = 0A to 2A
SYNC = GND, Io = 0A to 2A
Line Regulation
Soft-Start Ramp Time Cycle
OVERCURRENT PROTECTION
Dynamic Current Limit ON-time
Dynamic Current Limit OFF-time
Peak Overcurrent Limit
t
OCON
t
OCOFF
I
pk1
I
pk2
Negative Current Limit
I
valley1
I
valley2
2.7
2.3
-2.2
-2.2
17
4
3.2
2.8
-1.6
-1.6
3.6
3.2
-1.0
-1.0
Clock
pulses
SS cycle
A
A
A
A
V
IN
= V
O
+ 0.5V to 5.5V (minimal 2.8V)
0.590
0.600
0.1
±1.5
±1
0.2
1.3
0.610
V
µA
%
%
%/V
ms
I
VIN
I
SD
SYNC = GND, EN1 = EN2 = V
IN
, f
SW
= 2.25MHz, no load at
the output
V
IN
= 5.5V, EN1 = EN2 = GND
2.0
2.5
2.4
0.86
6.5
1.00
12.0
2.8
V
V
mA
µA
SYMBOL
TEST CONDITIONS
MIN
(Note
6)
TYP
MAX
(Note
6)
UNIT
Electrical Specifications
FN7908 Rev 3.00
November 30, 2016
Page 5 of 17
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