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CS230001-CZZ

Description
Timers u0026 Support Products IC Clock BW1Hz w/ 1x 2x 4x 8x
Categorylogic    logic   
File Size59KB,4 Pages
ManufacturerCirrus Logic
Websitehttp://www.cirrus.com
Environmental Compliance
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CS230001-CZZ Overview

Timers u0026 Support Products IC Clock BW1Hz w/ 1x 2x 4x 8x

CS230001-CZZ Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Parts packaging codeMSOP
package instructionLEAD FREE, MSOP-10
Contacts10
Reach Compliance Codecompliant
seriesS
Input adjustmentSTANDARD
JESD-30 codeS-PDSO-G10
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals10
Actual output times
Maximum operating temperature70 °C
Minimum operating temperature-10 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeSQUARE
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
surface mountYES
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
minfmax75 MHz
Base Number Matches1
CS2300-01
1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery 750 kHz to 30 MHz Clock
Source
Internal LCO Reference Clock
1 Hz Loop Filter Bandwidth
Selectable Multiplication Factors
– 1x, 2x, 4x, and 8x
Output Enable Pin
Lock Indicator
Minimal Board Space Required
– No External Analog Loop-filter
Components
Ordering Information
The CS2300-01 is available in a 10-pin MSOP package
in Commercial (-10°C to +70°C) grade. Customer de-
velopment kits are also available for custom device
prototyping and device evaluation. Please see
“Order-
ing Information” on page 2
for complete details.
Pin-Out Diagram
VD
GND
CLK_OUT
LOCK
CLK_IN
1
2
3
4
5
10
9
8
7
6
M0
M1
OUT_EN
FILTN
FILTP
General Description
The CS2300-01 is an extremely versatile system clock-
ing device that utilizes a programmable phase lock loop.
The CS2300-01 is based on a hybrid analog-digital PLL
architecture comprised of a unique combination of a
Delta-Sigma Fractional-N Frequency Synthesizer and a
Digital PLL. This architecture allows for generation of a
low-jitter clock relative to an external noisy synchroniza-
tion clock with frequencies as low as 750 kHz. The
CS2300-01 is a CS2300-OTP device that has been pre-
configured at the factory. There are three hardware con-
figuration pins available for mode and feature selection.
Hardware Controls Settings
M1
0
0
1
1
M0
0
1
0
1
PLL_OUT
1x CLK_IN
2x CLK_IN
4x CLK_IN
8x CLK_IN
OUT_EN
0
1
CLK_OUT
Enabled
High Impedance
FILTP
0.1 µF
LOCK
FILTN
LCO
PLL Lock
Indicator
6 MHz to 75 MHz
PLL Output
Output
Enable/Disable
Fractional-N
Frequency Synthesizer
M[1:0]
00=1x
01=2x
10=4x
11=8x
Output to Input
Clock Ratio
CLK_OUT
Ratio Selection
M1
M0
N
OUT_EN
750 kHz to 30 MHz
Frequency Reference
CLK_IN
1 Hz BW Digital PLL &
Fractional N Logic
VD
0.1 µF
1 µF
3.3 V
GND
Advance Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 2008
(All Rights Reserved)
AUG '08
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