Programmable Almost-Empty and Almost-Full flags can be set
to any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in the 32-pin plastic leaded chip carrier (PLCC) and
32-pin Thin Quad Flat Pack (TQFP)
For through-hole product please see the IDT72420/72200/72210/
72220/72230/72240 data sheet
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. These devices have a 64, 256, 512, 1,024,
2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are
applicable for a wide variety of data buffering needs such as graphics, local area
networks and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).
Data is written into the Synchronous FIFO on every rising clock edge when
the write enable pins are asserted. The output port is controlled by another clock
pin (RCLK) and two read enable pins (REN1,
REN2).
The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An output enable pin
(OE) is provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for
PAE
and
PAF,
respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the load pin (LD).
These FIFOs are fabricated using high-speed submicron CMOS technology.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
D
0
- D
8
LD
INPUT REGISTER
OFFSET REGISTER
EF
PAE
PAF
FF
WRITE CONTROL
LOGIC
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9
FLAG
LOGIC
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
OE
Q
0
- Q
8
2655 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.
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FPGA/CPLD
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