FDC37N869
5V and 3.3V Super I/O Controller with Infrared Support for
Portable Applications
FEATURES
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PC 99 Compliant
5 Volt and 3.3 Volt Operation
Intelligent Auto Power Management
16 Bit Address Qualification
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with
SMSC’s Proprietary 82077AA Compatible
Core
- Supports One Floppy Drive Directly
- Configurable Open Drain/Push-Pull Output
Drivers
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Power-Down Modes for
Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- Swap Drives A and B
- Non-Burst Mode DMA Option
- 48 Base I/O Address, 15 IRQ and 4 DMA
Options
- Forceable Write Protect and Disk Change
Controls
Floppy Disk Available on Parallel Port Pins
ACPI Compliant
Enhanced Digital Data Separator
- 2Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
Serial Ports
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
Infrared Communications Controller
- IrDA v1.1 (4Mbps), HPSIR, ASKIR, Consumer
IR Support
- 2 IR Ports
- 96 Base I/O Address, 15 IRQ Options and 4
DMA Options
Multi-Mode Parallel Port with ChiProtect
- Standard Mode
- IBM PC/XT, PC/AT, and PS/2 Compatible Bi-
directional Parallel Port
- Enhanced Parallel Port (EPP) Compatible
- EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
- Enhanced Capabilities Port (ECP)
Compatible (IEEE 1284 Compliant)
- Incorporates ChiProtect Circuitry for Protection
Against Damage Due to Printer Power-On
- 192 Base I/O Address, 15 IRQ and 4 DMA
Options
Game Port Select Logic
- 48 Base I/O Addresses
General Purpose Address Decoder
- 16-Byte Block Decode
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ORDERING INFORMATION
Order Number: FDC37N869TQFP
100 Pin TQFP Package
SMSC DS – FDC37N869
11/09/2000
© 2000 STANDARD MICROSYSTEMS CORPORATION (SMSC)
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, ChiProtect, SuperCell and Multi-Mode are
trademarks of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit
diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is
assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact
your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey
to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional
on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the
date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the
product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed,
intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or
severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be
fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by
visiting SMSC’s website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES
ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT
ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS – FDC37N869
Page 2
Rev. 11/09/2000
GENERAL DESCRIPTION
The SMSC FDC37N869 is a 5v/3.3v PC 99-compliant Super I/O Controller with Infrared support. The FDC37N869
utilizes SMSC’s proven SuperCell technology and is optimized for motherboard applications. The FDC37N869
incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16-byte data FIFO,
two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support,
game port chip select logic and one floppy direct drive support. The FDC37N869 does not require any external
filter components, is easy to use and offers lower system cost and reduced board area. The FDC37N869 is
software and register compatible with SMSC’s proprietary 82077AA core.
The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data
overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC’s patented data
separator technology allowing for ease of testing and use. The FDC37N869 supports both 1Mbps and 2Mbps data
rates and vertical recording operation at 1Mbps Data Rate.
The FDC37N869 also features a full 16-bit internally decoded address bus, a Serial IRQinterface with PCI
nCLKRUN support, relocatable configuration ports and four DMA channel options.
Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial
Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp, Apple Newton,
and other PDAs), as well as Consumer IR.
The parallel port and the game port select logic are compatible with IBM PC/AT architectures. The parallel port
ChiProtect circuitry prevents damage caused by an attached powered printer when the FDC37N869 is not
powered.
The FDC37N869 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power
down modes. The FDC37N869 also features Software Configurable Logic (SCL) for ease of use. SCL allows
programmable system configuration of key functions such as the FDC, parallel port, and UARTs.
SMSC DS – FDC37N869
Page 3
Rev. 11/09/2000
TABLE OF CONTENTS
GENERAL DESCRIPTION ...................................................................................................................3
PIN CONFIGURATION ........................................................................................................................8
PIN DESCRIPTION .............................................................................................................................9
BUFFER TYPE PER PIN..................................................................................................................9
B
UFFER
T
YPE
S
UMMARY
.................................................................................................................... 15
O
UTPUT
D
RIVERS
.............................................................................................................................. 15
FUNCTIONAL DESCRIPTION............................................................................................................ 17
H
OST
P
ROCESSOR
I
NTERFACE
............................................................................................................. 17
FLOPPY DISK CONTROLLER........................................................................................................... 17
M
ODES
O
F
O
PERATION
...................................................................................................................... 17
Floppy Modes...........................................................................................................................
17
Interface Modes.........................................................................................................................
18
F
LOPPY
D
ISK
C
ONTROLLER
I
NTERNAL
R
EGISTERS
.................................................................................... 18
STATUS REGISTER A (SRA).....................................................................................................
18
STATUS REGISTER B (SRB)
..................................................................................................... 21
DIGITAL OUTPUT REGISTER (DOR)...........................................................................................
23
TAPE DRIVE REGISTER (TDR)
.................................................................................................. 24
MAIN STATUS REGISTER (MSR)
.............................................................................................. 25
DATA RATE SELECT REGISTER (DSR)
.................................................................................... 26
DATA REGISTER (FIFO)............................................................................................................
29
DIGITAL INPUT REGISTER (DIR)
................................................................................................ 29
CONFIGURATION CONTROL REGISTER (CCR)
.......................................................................... 31
S
TATUS
R
EGISTER
E
NCODING
.............................................................................................................. 32
R
ESET
............................................................................................................................................ 33
RESET Pin (Hardware Reset)
..................................................................................................... 34
DOR Reset vs. DSR Reset (Software Reset).................................................................................
34
DMA T
RANSFERS
............................................................................................................................. 34
C
ONTROLLER
P
HASES
....................................................................................................................... 34
Command Phase........................................................................................................................ 34
Execution Phase
....................................................................................................................... 34
Result Phase
............................................................................................................................. 35
C
OMMAND
S
ET
/D
ESCRIPTIONS
............................................................................................................. 36
I
NSTRUCTION
S
ET
.............................................................................................................................. 38
D
ATA
T
RANSFER
C
OMMANDS
.............................................................................................................. 46
Read Data
................................................................................................................................. 46
Read Deleted Data.....................................................................................................................
48
Read A Track
............................................................................................................................ 48
Write Data.................................................................................................................................
49
Write Deleted Data
.................................................................................................................... 50
Verify......................................................................................................................................... 50
Format A Track.........................................................................................................................
51
C
ONTROL
C
OMMANDS
....................................................................................................................... 52
Read ID..................................................................................................................................... 52
Recalibrate................................................................................................................................
52
Seek
......................................................................................................................................... 53
Sense Interrupt Status ................................................................................................................ 53
Sense Drive Status....................................................................................................................
54
Specify
..................................................................................................................................... 54
SMSC DS – FDC37N869
Page 4
Rev. 11/09/2000
Configure..................................................................................................................................
54
Version
..................................................................................................................................... 55
Relative Seek ............................................................................................................................. 55
Perpendicular Mode..................................................................................................................
56
LOCK........................................................................................................................................
57
ENHANCED DUMPREG
............................................................................................................. 57
COMPATIBILITY ............................................................................................................................ 57
P
ARALLEL
P
ORT
F
LOPPY
D
ISK
C
ONTROLLER
.......................................................................................... 57
SERIAL PORT (UART) ...................................................................................................................... 59
R
EGISTER
D
ESCRIPTION
...................................................................................................................... 59
RECEIVE BUFFER REGISTER (RB)............................................................................................
59
TRANSMIT BUFFER REGISTER (TB)
......................................................................................... 59
INTERRUPT ENABLE REGISTER (IER).......................................................................................
59
INTERRUPT IDENTIFICATION REGISTER (IIR)
............................................................................ 60
FIFO CONTROL REGISTER (FCR)..............................................................................................
62
LINE CONTROL REGISTER (LCR)..............................................................................................
63
MODEM CONTROL REGISTER (MCR)
....................................................................................... 64
LINE STATUS REGISTER (LSR)
................................................................................................ 65
MODEM STATUS REGISTER (MSR)..........................................................................................
66
SCRATCHPAD REGISTER (SCR)
............................................................................................... 67
PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES
........................................... 67
The Affects of RESET on the UART Registers............................................................................
68
FIFO I
NTERRUPT
M
ODE
O
PERATION
...................................................................................................... 68
FIFO P
OLLED
M
ODE
O
PERATION
......................................................................................................... 69
N
OTES
O
N
S
ERIAL
P
ORT
FIFO M
ODE
O
PERATION
................................................................................... 70
GENERAL.................................................................................................................................
70
TX AND RX FIFO OPERATION...................................................................................................
71
INFRARED INTERFACE .................................................................................................................... 71
I
R
DA SIR/FIR
AND
ASKIR ................................................................................................................ 71
C
ONSUMER
IR.................................................................................................................................. 72
H
ARDWARE
I
NTERFACE
...................................................................................................................... 72
IR H
ALF
D
UPLEX
T
URNAROUND
D
ELAY
T
IME
........................................................................................... 72
PARALLEL PORT............................................................................................................................. 74
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES........................................................ 75
DATA PORT..............................................................................................................................
75
STATUS PORT..........................................................................................................................
75
CONTROL PORT
....................................................................................................................... 76
EPP ADDRESS PORT................................................................................................................
77
EPP DATA PORT 0....................................................................................................................
77
EPP DATA PORT 1....................................................................................................................
77
EPP DATA PORT 2....................................................................................................................
77
EPP DATA PORT 3....................................................................................................................
77
EPP 1.9 OPERATION .................................................................................................................... 77
Software Constraints.................................................................................................................
78
EPP 1.9 Write............................................................................................................................
78
EPP 1.9 Read
............................................................................................................................ 78
EPP 1.7 OPERATION .................................................................................................................... 79
Software Constraints.................................................................................................................
79
EPP 1.7 Write............................................................................................................................
79
EPP 1.7 Read
............................................................................................................................ 79
EXTENDED CAPABILITIES PARALLEL PORT.................................................................................. 81
Vocabulary
............................................................................................................................... 81
ISA IMPLEMENTATION STANDARD..........................................................................................
82
SMSC DS – FDC37N869
Page 5
Rev. 11/09/2000
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