DS1004M-3 datasheet, PDF - EEWORLD Datasheet

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DS1004M-3: DescriptionDelay Lines / Timing Elements; Categorylogic logic; File Size53KB，6 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1004M-3 Overview

Delay Lines / Timing Elements

DS1004M-3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, MS-001AB, DIP-8
Contacts	8
Reach Compliance Code	not_compliant
Other features	INPUT TO 1ST TAP DELAY = 5NS
series	CMOS
Input frequency maximum value (fmax)	36.7647 MHz
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.375 mm
Logic integrated circuit type	SILICON DELAY LINE
Humidity sensitivity level	1
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP8,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Maximum supply current (ICC)	75 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	17 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
Total delay nominal (td)	17 ns
width	7.62 mm

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DS1004

5-Tap High Speed

Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon timing circuit

Five delayed clock phases per input

Precise tap-to-tap nominal delay tolerances of

±0.75 and ±1 ns

Input-to-tap 1 delay of 5 ns

Nominal Delay tolerances of ±1.5 ns

Leading and trailing edge precision preserves

the input symmetry

CMOS design with TTL compatibility

Standard 8-pin DIP and 150 mil 8-pin SOIC

Vapor phase, IR and wave solderable

Available in Tape and Reel

PIN ASSIGNMENT

TAP 2

TAP 4

GND

TAP 1

TAP 3

TAP 5

DS1004M 8-Pin DIP (300-mil)

See Mech. Drawings Section

TAP 2

TAP 4

GND

TAP 1

TAP 3

TAP 5

DS1004Z 8-Pin SOIC (150-mil)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1-5

GND

- TAP Output Number

- +5V Supply

- Ground

- Input

DESCRIPTION

The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a

standard part family. The device is Dallas Semiconductor’s fastest 5-tap delay line. It is available in a

standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing edge

accuracies and has the inherent reliability of an all-silicon delay line solution.

The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum

input-to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns.

See Table 1 for details. Input to Tap Tolerance over temperature and voltage is

±1.5

ns in addition to the

nominal delay tolerance. Nominal tap-to-tap tolerances range from

±0.75

ns to

±1.0

ns. Each output is

capable of driving up to 10 LS loads.

For customers needing non-standard delay values, the Late Package Program (LPP) is available.

Customers may contact Dallas Semiconductor at (972) 371–4348 for further details.

1 of 6

092500

DS1004M-3 Related Products

	DS1004M-3	DS1004M-2
Description	Delay Lines / Timing Elements
Is it Rohs certified?	incompatible	incompatible
Maker	Maxim	Maxim
Parts packaging code	DIP	DIP
package instruction	0.300 INCH, PLASTIC, MS-001AB, DIP-8	0.300 INCH, PLASTIC, MS-001AB, DIP-8
Contacts	8	8
Reach Compliance Code	not_compliant	not_compliant
Other features	INPUT TO 1ST TAP DELAY = 5NS	INPUT TO 1ST TAP DELAY = 5NS
series	CMOS	CMOS
Input frequency maximum value (fmax)	36.7647 MHz	48.0769 MHz
JESD-30 code	R-PDIP-T8	R-PDIP-T8
JESD-609 code	e0	e0
length	9.375 mm	9.375 mm
Logic integrated circuit type	SILICON DELAY LINE	SILICON DELAY LINE
Humidity sensitivity level	1	1
Number of functions	1	1
Number of taps/steps	5	5
Number of terminals	8	8
Maximum operating temperature	70 °C	70 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP
Encapsulate equivalent code	DIP8,.3	DIP8,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	240	240
power supply	5 V	5 V
Maximum supply current (ICC)	75 mA	75 mA
programmable delay line	NO	NO
Prop。Delay @ Nom-Sup	17 ns	13 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	4.572 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	20	20
Total delay nominal (td)	17 ns	13 ns
width	7.62 mm	7.62 mm

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