Programmable System-on-Chip (PSoC )
General Description
PSoC
®
5LP: CY8C56LP Family
Datasheet
®
PSoC
®
5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and
a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through:
32-bit ARM
®
Cortex
®
-M3 core plus DMA controller and digital filter processor, at up to 80 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Analog peripherals
Voltage range: 1.71 to 5.5 V, up to 6 power domains
[1]
Temperature range (ambient): –40 to 85 °C
Extended temperature parts: –40 to 105 °C
DC to 80-MHz operation
Power modes
• Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Performance
32-bit ARM Cortex-M3 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
24-bit 64-tap fixed-point digital filter processor (DFB)
Memories
Up to 256 KB program flash, with cache and security features
Up to 32 KB additional flash for error correcting code (ECC)
Up to 64 KB RAM
2 KB EEPROM
Digital peripherals
Four 16-bit timer, counter, and PWM (TCPWM) blocks
2
I C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral inter-
face (TID#10840032) using internal oscillator
[2]
Full CAN 2.0b, 16 Rx, 8 Tx buffers
20 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I
2
C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
Configurable 8- to 12-bit delta-sigma ADC
Up to two 12-bit SAR ADCs
Four 8-bit DACs
Four comparators
Four opamps
Four programmable analog blocks, to create:
• Programmable gain amplifier (PGA)
• Transimpedance amplifier (TIA)
• Mixer
• Sample and hold circuit
®
CapSense support, up to 62 sensors
1.024 V ±0.1% internal voltage reference
Versatile I/O system
48 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire
viewer (SWV), and Traceport (5-wire) interfaces
ARM debug and trace modules embedded in the CPU core
2
Bootloader programming through I C, SPI, UART, USB, and
other interfaces
Package options: 68-pin QFN,100-pin TQFP, and 99-pin CSP
Programmable clocking
Development support with free PSoC Creator™ tool
3- to 74-MHz internal oscillator, 1% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 80 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free GCC compiler, supports Keil/ARM MDK
compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See
Ordering Information
on page 119 for details.
Cypress Semiconductor Corporation
Document Number: 001-84935 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 20, 2017
PSoC
®
5LP: CY8C56LP Family
Datasheet
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP.
Following is an abbreviated list for PSoC 5LP:
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
Development Kits:
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes and
code examples
covering a broad range
of topics, from basic to advanced level. Recommended appli-
cation notes for getting started with PSoC 5LP are:
AN77759:
Getting Started With PSoC 5LP
AN77835:
PSoC 3 to PSoC 5LP Migration Guide
AN61290:
Hardware Design Considerations
AN57821:
Mixed Signal Circuit Board Layout
AN58304:
Pin Selection for Analog Designs
AN81623:
Digital Design Best Practices
AN73854:
Introduction To Bootloaders
CY8CKIT-059
is a low-cost platform for prototyping, with a
unique snap-away programmer and debugger on the USB
connector.
CY8CKIT-050
is designed for analog performance, for devel-
oping high-precision analog, low-power, and low-voltage ap-
plications.
CY8CKIT-001
provides a common development platform for
any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP
families of devices.
The
MiniProg3
device provides an interface for flash pro-
gramming and debug.
Technical Reference Manuals (TRM)
Architecture TRM
Registers TRM
Programming Specification
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
5
Document Number: 001-84935 Rev. *L
Page 2 of 131
4
PSoC
®
5LP: CY8C56LP Family
Datasheet
Contents
1. Architectural Overview ................................................. 4
2. Pinouts ........................................................................... 6
3. Pin Descriptions .......................................................... 11
4. CPU ............................................................................... 12
4.1 ARM Cortex-M3 CPU ...........................................12
4.2 Cache Controller ..................................................14
4.3 DMA and PHUB ...................................................15
4.4 Interrupt Controller ...............................................17
5. Memory ......................................................................... 19
5.1 Static RAM ...........................................................19
5.2 Flash Program Memory ........................................19
5.3 Flash Security .......................................................19
5.4 EEPROM ..............................................................19
5.5 Nonvolatile Latches (NVLs) ..................................20
5.6 External Memory Interface ...................................21
5.7 Memory Map ........................................................22
6. System Integration ...................................................... 23
6.1 Clocking System ...................................................23
6.2 Power System ......................................................26
6.3 Reset ....................................................................30
6.4 I/O System and Routing .......................................32
7. Digital Subsystem ....................................................... 38
7.1 Example Peripherals ............................................39
7.2 Universal Digital Block ..........................................40
7.3 UDB Array Description .........................................44
7.4 DSI Routing Interface Description ........................44
7.5 CAN ......................................................................46
7.6 USB ......................................................................47
7.7 Timers, Counters, and PWMs ..............................48
7.8 I
2
C ........................................................................48
7.9 Digital Filter Block .................................................50
8. Analog Subsystem ...................................................... 50
8.1 Analog Routing .....................................................52
8.2 Delta-sigma ADC ..................................................54
8.3 Successive Approximation ADCs .........................55
8.4 Comparators .........................................................55
8.5 Opamps ................................................................57
8.6 Programmable SC/CT Blocks ..............................57
8.7 LCD Direct Drive ..................................................58
8.8 CapSense .............................................................59
8.9 Temp Sensor ........................................................59
8.10 DAC ....................................................................59
8.11 Up/Down Mixer ...................................................60
8.12 Sample and Hold ................................................61
9. Programming, Debug Interfaces, Resources ............ 61
9.1 JTAG Interface .....................................................62
9.2 SWD Interface ......................................................63
9.3 Debug Features ....................................................64
9.4 Trace Features .....................................................64
9.5 SWV and TRACEPORT Interfaces ......................64
9.6 Programming Features .........................................64
9.7 Device Security ....................................................64
9.8 CSP Package Bootloader .....................................65
10. Development Support ............................................... 65
10.1 Documentation ...................................................65
10.2 Online .................................................................65
10.3 Tools ...................................................................65
11. Electrical Specifications ........................................... 66
11.1 Absolute Maximum Ratings ................................66
11.2 Device Level Specifications ................................67
11.3 Power Regulators ...............................................71
11.4 Inputs and Outputs .............................................75
11.5 Analog Peripherals .............................................83
11.6 Digital Peripherals ............................................104
11.7 Memory ............................................................108
11.8 PSoC System Resources .................................112
11.9 Clocking ............................................................115
12. Ordering Information ............................................... 119
12.1 Part Numbering Conventions ...........................120
13. Packaging ................................................................. 121
14. Acronyms ................................................................. 124
15. Reference Documents ............................................. 125
16. Document Conventions .......................................... 126
16.1 Units of Measure ..............................................126
Document History Page ................................................ 127
Sales, Solutions, and Legal Information .....................
Worldwide Sales and Design Support......................
Products ...................................................................
PSoC® Solutions .....................................................
Cypress Developer Community................................
Technical Support ....................................................
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Document Number: 001-84935 Rev. *L
Page 3 of 131
PSoC
®
5LP: CY8C56LP Family
Datasheet
1. Architectural Overview
Introducing the CY8C56LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5LP platform. The CY8C56LP family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
GPIOs
Sequencer
Usage Example for UDB
4- 25 MHz
( Optional
)
System Wide
Resources
Xtal
Osc
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit
Timer
UDB
Quadrature Decoder
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
CAN 2.0
I2C
Master/
Slave
SIO
22
UDB
UDB
Clock Tree
UDB
I 2C Slave
UDB
UDB
8- Bit SPI
UDB
12- Bit SPI
UDB
8- Bit
Timer
Logic
UDB
GPIOs
UDB
UDB
UDB
UDB
IMO
4x
Timer
Counter
PWM
FS USB
2.0
USB
PHY
Logic
UDB
UART
UDB
UDB
12- Bit PWM
UDB
UDB
UDB
32.768 KHz
( Optional
)
RTC
Timer
System Bus
Memory System
WDT
and
Wake
GPIOs
EEPROM
SRAM
CPU System
Cortex M3CPU
Interrupt
Controller
Program &
Debug
Program
Debug &
Trace
EMIF
ILO
FLASH
Cache
Controller
PHUB
DMA
Boundary
Scan
Clocking System
Power Management
System
SIOs
LCD Direct
Drive
Digital
Filter
Block
Analog System
ADCs
2x
SAR
ADC
+
4x
Opamp
-
POR and
LVD
Sleep
Power
1.71 to
5.5 V
1.8 V LDO
SMP
4 x SC / CT Blocks
(TIA, PGA, Mixer etc)
3 per
Opamp
4x DAC
CapSense
1x
Del Sig
ADC
4x
CMP
-
0. 5 to 5.5 V
( Optional
)
Figure 1-1
illustrates the major components of the CY8C56LP
family. They are:
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals. In
addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C56LP family these blocks can include four 16-bit timer,
counter, and PWM blocks; I
2
C slave, master, and multi-master;
Full-Speed USB; and Full CAN 2.0.
Page 4 of 131
Document Number: 001-84935 Rev. *L
GPIOs
Temperature
Sensor
+
GPIOs
GPIOs
GPIOs
PSoC
®
5LP: CY8C56LP Family
Datasheet
For more details on the peripherals see the
“Example
Peripherals”
section on page 39 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 38 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1% error
over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Analog mixers
Voltage references
ADCs
DACs
DFB
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the
“Analog Subsystem”
section on page 50 of this
datasheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 80 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. You can enable an ECC
for high reliability applications. A powerful and flexible protection
model secures the user's sensitive information, allowing
selective memory block locking for read and write protection.
Two KB of byte-writable EEPROM is available on-chip to store
application data. Additionally, selected configuration options
such as boot speed and pin drive mode are stored in nonvolatile
memory. This allows settings to activate immediately after power
on reset (POR).
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive, CapSense, flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow V
OH
to be set independently of VDDIO when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I
2
C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with FS USB the USB physical
interface is also provided (USBIO). When not using USB these
pins may also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the
“I/O System and Routing”
section on page 32 of this
datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 74 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 80 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
Some CY8C56LP devices offer a fast, accurate, configurable
delta-sigma ADC with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
The CY8C56LP family also offers one or two successive
approximation register (SAR) ADCs, depending on device
selected. Featuring 12-bit conversions at up to 1 M samples per
second, they also offer low nonlinearity and offset errors and
SNR better than 70 dB. They are well suited for a variety of
higher speed analog applications.
The output of either ADC can optionally feed the programmable
DFB via DMA without CPU intervention. You can configure the
DFB to perform IIR and FIR digital filters and several user
defined custom functions. The DFB can implement filters with up
to 64 taps. It can perform a 48-bit multiply-accumulate (MAC)
operation in one clock cycle.
Four high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Document Number: 001-84935 Rev. *L
Page 5 of 131
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