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854S1208AYILF

Description
USB Interface IC USB to Basic Serial UART IC SSOP-16
Categorysemiconductor    Analog mixed-signal IC   
File Size1MB,19 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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854S1208AYILF Overview

USB Interface IC USB to Basic Serial UART IC SSOP-16

854S1208AYILF Parametric

Parameter NameAttribute value
Product CategoryClock Drivers & Distribution
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Package / CasePTQFP-48
PackagingTray
Height1 mm
Length7 mm
Moisture SensitiveYes
Factory Pack Quantity250
Width7 mm
Differential-to-LVDS Fanout Buffer w/Divider
and Glitchless Switch
ICS854S1208I
DATA SHEET
General Description
The
ICS854S1208I is a low skew, 8 output LVDS Fanout Buffer with
selectable divider. The ICS854S1208I has 2 selectable inputs that
accept a variety of differential input types. The device provides the
capability to suppress any glitch at the outputs of the device during
an input clock switch to enhance clock redundancy in fault tolerant
applications.
The divide select inputs, DIV_SELA and DIV_SELB, control the
output frequency of each bank. The output banks can be
independently selected for ÷1 or ÷2 operation. The output enable
pins assigned to each output, support enabling and disabling each
output individually.
The ICS854S1208I is characterized at full 3.3V or 2.5V output
operating supply modes. Guaranteed output and part-to-part skew
characteristics make the ICS854S1208I ideal for high performance
applications.
Features
Eight differential LVDS output pairs
Each output has individual synchronous output enable
Two selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HCSL
Maximum output frequency: 1.5GHz
Independent bank control for ÷1 or ÷2 operation
Glitchless output behavior during input switch
Output skew: 40ps (maximum)
Bank skew: 35ps (maximum)
Full 3.3V or 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Supply Mode Operation Table
3.3V Operation
V
DD
= 3.3V
V
TAP
= Float
2.5V Operation
V
DD
= 2.5V
V
TAP
= 2.5V
V
DD
DIV_SELA
V
TAP
CLK0
nCLK0
GND
CLK_SEL
nCLK1
CLK1
GND
DIV_SELB
V
DD
Pin Assignment
GND
QA2
nQA2
QA3
nQA3
V
DD
V
DD
nQB3
QB3
nQB2
QB2
GND
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
nQA1
V
DD
V
DD
nQB1
QB1
nQB0
QB0
GND
GND
QA0
nQA0
QA1
V
DD
OEB0
OEB1
OEB2
OEB3
GND
V
DD
OEA3
OEA2
OEA1
OEA0
V
DD
ICS854S1208I
48-Pin TQFP, E-Pad
7mm x 7mm x 1mm package body
Y Package
Top View
ICS854S1208AYI REVISION A APRIL 27, 2012
1
©2012 Integrated Device Technology, Inc.
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