XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
MAY 2007
REV. 1.0.1
GENERAL DESCRIPTION
The XR16L570 (L570) is a 1.62 to 5.5 volt Universal
Asynchronous Receiver and Transmitter (UART) with 5 volt
tolerant inputs and a reduced pin count. It is software
compatible to industry standard 16C450, 16C550,
ST16C580, ST16C650A, XR16C850 and XR16L580
UARTs. It has 16 bytes of TX and RX FIFOs and is capable
of operating with a serial data rate of up to 4 Mbps at 5V, 3
Mbps at 3.3V,1 Mbps at 2.5V and 750 Kbps at 1.8V. The
internal registers are compatible to the 16C550 register set
plus enhanced registers for additional features to support
today’s high bandwidth data communication needs. The
enhanced features include
automatic hardware and
software flow control to prevent data loss, selectable RX
and TX trigger levels for more efficient interrupt service,
wireless infrared (IrDA) encoder/decoder for wireless
applications and a unique Power-Save mode to increase
battery operating time. The device comes in 32-QFN and
24-QFN packages in industrial temperature range.
FEATURES
•
Smallest Full Featured UART
•
1.62V to 5.5V Supply Voltage
•
5V Tolerant Inputs (except XTAL1/CLK)
•
’0 ns’ Address Hold Time (T
AH
and T
ADH
)
•
Software Compatible to industry standard
16C550, ST16C580,
XR16L580
ST16C650A,
16C450,
XR16C850 and
APPLICATIONS
•
Handheld Terminals and Tablets
•
Handheld Computers
•
Wireless Portable Point-of-Sale Terminals
•
Cellular Phones DataPort
•
GPS Devices
•
Personal Digital Assistants Modules
•
Battery Operated Instruments
F
IGURE
1. B
LOCK
D
IAGRAM
•
16-byte Transmit FIFO
•
16-byte Receive FIFO with Errors Flags
•
Selectable RX and TX FIFO Trigger Levels
•
Automatic Hardware (RTS/CTS) Flow Control
•
Automatic Software (Xon/Xoff) Flow Control
•
Up to 4 Mbps data rate at 5.0V Operation
•
Up to 3 Mbps data rate at 3.3V Operation
•
Up to 1 Mbps data rate at 2.5V Operation
•
Up to 750 Kbps data rate at 1.8V Operation
•
Infrared (IrDA) Encoder/Decoder
•
Complete Modem Interface
•
Power-Save Mode to conserve battery power
•
Sleep Mode with Wake-up Interrupt
•
Very small packages: 24-QFN (4x4x0.9mm) and 32-QFN
(5x5x0.9mm)
•
Industrial Temperature Grade(-40 to +85
o
C)
PwrSave
A2:A0
D7:D0
IOR#
IOW#
CS#
INT
RESET
*5 V Tolerant Inputs
(Except for CLK)
UART
UART
Regs
TX & RX
VCC
(1.62 to 5.5 V)
GND
TX
RX
RTS#
CTS#
DTR#
DSR#
CD#
RI#
16 Byte TX FIFO
IR
ENDEC
Data Bus
Interface
BRG 16 Byte RX FIFO
Clock Buffer
XTAL1 (CLK)
XTAL2
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.1
F
IGURE
2. P
ACKAGE AND
P
IN
O
UT
(24-
PIN
QFN P
ACKAGE
)
CTS#
RESET
DTR#
RTS#
INT
Reset
CTS#
RTS#
24 23 22 21 20 19 18 17
INT
A0
A1
A0
A1
A2
16
15
14
13
12
11
10
9
NC
NC
IOR#
GND
IOW#
XTAL2
XTAL1
NC
18 17 16 15 14 13
VCC 19
12
D0 20
11
D1 21
D2 22
D3 23
D4 24
1
D5
2
D6
3
D7
4
RX
5
TX
24-pin QFN
10
9
8
7
6
CS#
A2
IOR#
GND
IOW#
CLK
PwrSave
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
25
26
27
28
29
30
31
32
32-pin QFN
1 2 3 4 5 6 7 8
D4
NC
D5
D6
D7
RX
TX
CS#
ORDERING INFORMATION
P
ART
N
UMBER
XR16L570IL24
XR16L570IL32
P
ACKAGE
24-pin QFN
32-pin QFN
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
2
XR16L570
REV. 1.0.1
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
PIN DESCRIPTIONS
Pin Descriptions
N
AME
24-QFN 32-QFN
T
YPE
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
12
13
14
3
2
1
24
23
22
21
20
11
17
18
19
5
4
3
1
32
31
30
29
14
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
the UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
This input is the read strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed by the address
lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it
on the rising edge.
This input is the write strobe (active low). The falling edge instigates the internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
This input is chip select (active low) to enable the device.
This output is the active high device interrupt output. The output state is defined by
the user through the software setting of MCR[3]. INT is set to the active mode when
MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a
logic 0. See MCR[3].
IOW#
9
12
I
CS#
INT
6
15
8
20
I
O
MODEM OR SERIAL I/O INTERFACE
TX
5
7
O
UART Transmit Data or infrared encoder data. Standard transmit and receive inter-
face is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during
reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when
MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it unconnected.
UART Receive Data or infrared receive data. Normal receive data input must idle at
logic 1 condition. The infrared receiver idles at logic 0.
UART Request-to-Send (active low) or general purpose output. This output must be
asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6].
UART Clear-to-Send (active low) or general purpose input. It can be used for auto
CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to
VCC when not used.
UART Data-Terminal-Ready (active low) or general purpose output.
This pin is not
available in the 24-QFN package.
UART Data-Set-Ready (active low) or general purpose input. This input should be
connected to VCC when not used. This input has no effect on the UART.
This pin is
not available in the 24-QFN package.
RX
RTS#
CTS#
4
16
18
6
21
24
I
O
I
DTR#
DSR#
-
-
22
25
O
I
3
XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.1
Pin Descriptions
N
AME
CD#
24-QFN 32-QFN
T
YPE
P
IN
#
P
IN
#
-
26
I
D
ESCRIPTION
UART Carrier-Detect (active low) or general purpose input. This input should be con-
nected to VCC when not used. This input has no effect on the UART.
This pin is not
available in the 24-QFN package.
UART Ring-Indicator (active low) or general purpose input. This input should be con-
nected to VCC when not used. This input has no effect on the UART.
This pin is not
available in the 24-QFN package.
RI#
-
27
I
ANCILLARY SIGNALS
XTAL1
(CLK)
XTAL2
PwrSave
8
-
7
10
11
-
I
O
I
Crystal or external clock input. This input is not 5V tolerant.
Crystal or buffered clock output. This output may be use to drive a clock buffer which
can drive other device(s).
This pin is not available in the 24-QFN package.
Power-Save (active high). This feature isolates the L570’s data bus interface from
the host preventing other bus activities that cause higher power drain during sleep
mode. See Sleep Mode with Auto Wake-up and Power-Save Feature section for
details.
This pin is not available in the 28-QFN package.
This input is the active high RESET signal.
A 40 ns minimum active pulse on this pin will reset the internal registers and all out-
puts of the UART. The UART transmitter output will be held at logic 1, the receiver
input will be ignored and outputs are reset during reset period (see UART Reset Con-
ditions).
1.62V to 5.5V power supply. All input pins, except CLK, are 5V tolerant.
Power supply common, ground.
The center pad on the backside of the QFN packages is metallic and should be con-
nected to GND on the PCB. The thermal pad size on the PCB should be the approxi-
mate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
RESET
17
23
I
VCC
GND
GND
19
10
Center
Pad
28
13
Center
Pad
Pwr
Pwr
Pwr
N
OTE
:
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
4
XR16L570
REV. 1.0.1
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
1.0 PRODUCT DESCRIPTION
The XR16L570 (L570) is an enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its
features set is compatible to the ST16C580 device and additionally offers Power-Save to isolate the data bus
interface during Sleep mode. The XR16L570 can operate from 1.62V to 5.5V with 5 volt tolerant inputs. The
configuration registers set is 16550 UART compatible for control, status and data transfer. Also, the L570 has
16-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, transmit and receive FIFO trigger levels, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4. The L570 is fabricated
using an advanced CMOS process.
Enhanced Features
The L570 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L570 is
designed to work with low supply voltage and high performance data communication systems, that require fast
data processing time. Increased performance is realized in the L570 by the transmit and receive FIFOs, FIFO
trigger level controls and automatic flow control mechanism. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time. In addition, the L570 provides the
Power-Save mode that drastically reduces the power consumption when the device is not used. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Bus Interface
The L570 provides a host interface that supports a microprocessor (CPU) data bus interface. The interface
allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CS# inputs for data bus
operation. See pin description section for details on all the control signals.
Data Rate
The L570 is capable of operation up to 4 Mbps at 5V, 3 Mbps at 3.3V, 1 Mbps at 2.5V and 750 Kbps at 1.8V
with 16X internal sampling clock rate by using an external clock source on the XTAL1 (CLK) pin.
Internal Enhanced Register Sets
The L570 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/
disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/
software flow control enable/disable, programmable baud rates, infrared encoder/decoder enable/disable,
modem interface controls and status, sleep mode and Power-Save mode (in the 24-QFN package) are all
standard features. Following a power on reset or an external reset, the registers defaults to the reset condition
and it is compatible with previous generation of UARTs, 16C450, 16C550, 16C580, 16L580, 16C650A and
16C850.
5
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