Programmable System-on-Chip (PSoC )
General Description
PSoC
®
4: 4200_BLE
Family Datasheet
®
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm
®
Cortex
®
-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4200_BL product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy
(BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic,
high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard communication and timing
peripherals. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Subsystem
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Capacitive Sensing
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48-MHz Arm Cortex-M0 CPU with single-cycle multiply and
DMA
Up to 256 KB of flash with Read Accelerator
Up to 32 KB of SRAM
BLE 4.2 support
2.4-GHz RF transceiver with 50-Ω antenna drive
Digital PHY
Link-Layer engine supporting master and slave modes
RF output power: –18 dBm to +3 dBm
RX sensitivity: –89 dBm
RX current: 18.7 mA
TX current: 15.6 mA at 0 dBm
RSSI: 1-dB resolution
Four opamps with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator modes, and ADC
input buffering capability. Can operate in Deep Sleep mode.
12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep mode
Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and data path
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and liquid tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning algorithm (SmartSense™)
LCD drive supported on all pins (common or segment)
Operates in Deep Sleep mode with four bits per pin memory
Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I
2
C, SPI, or UART
functionality
Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
7 mm × 7 mm 56-pin QFN package
76-ball CSP package
68-ball CSP package
Any GPIO pin can be CapSense, LCD, analog, or digital
Two overvoltage-tolerant (OVT) pins; drive modes, strengths,
and slew rates are programmable
Integrated Design Environment (IDE) provides schematic
design entry and build (with analog and digital automatic
routing)
API components for all fixed-function and programmable
peripherals
After schematic entry, development can be done with
Arm-based industry-standard development tools
BLE Radio and Subsystem
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Segment LCD Drive
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Serial Communication
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Timing and Pulse-Width Modulation
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Programmable Analog
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Up to 36 Programmable GPIOs
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Programmable Digital
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PSoC Creator™ Design Environment
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Power Management
Active mode: 1.7 mA at 3-MHz flash program execution
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Deep Sleep mode: 1.5 µA with watch crystal oscillator (WCO)
on
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Hibernate mode: 150 nA with RAM retention
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Stop mode: 60 nA
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Industry-Standard Tool Compatibility
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Cypress Semiconductor Corporation
Document Number: 002-23053 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 22, 2018
PSoC
®
4: 4200_BLE
Family Datasheet
More Information
Cypress provides a wealth of data at
http://www.cypress.com
to
help you to select the right PSoC device for your design, and to
help you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the intro-
duction page for
Bluetooth® Low Energy (BLE) Products.
Following is an abbreviated list for PRoC BLE:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PRoC BLE,
PSoC 4 BLE, PSoC 5LP In addition, PSoC Creator includes a
device selection tool.
■
Application Notes: Cypress offers a large number of PSoC
application notes coverting a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PRoC BLE are:
❐
AN94020:
Getting Started with PRoC BLE
❐
AN97060:
PSoC 4 BLE and PRoC BLE - Over-The-Air (OTA)
Device Firmware Upgrade (DFU) Guide
❐
AN91184:
PSoC 4 BLE - Designing BLE Applications
❐
AN91162:
Creating a BLE Custom Profile
❐
AN91445:
Antenna Design and RF Layout Guidelines
❐
AN96841:
Getting Started With EZ-BLE Module
AN85951:
PSoC 4 CapSense Design Guide
❐
AN95089:
PSoC 4/PRoC BLE Crystal Oscillator Selection
and Tuning Techniques
❐
AN92584:
Designing for Low Power and Estimating Battery
Life for BLE Applications
■
Technical Reference Manual (TRM) is in two documents:
❐
Architecture TRM
details each PRoC BLE functional block
❐
Registers TRM
describes each of the PRoC BLE registers
■
Development Kits:
❐
CY8CKIT-042-BLE-A
Pioneer Kit, is a flexible, Arduino-com-
patible, Bluetooth LE development kit for PSoC 4 BLE and
PRoC BLE.
❐
CY8CKIT-142,
PSoC 4 BLE Module, features a PSoC 4 BLE
device, two crystals for the antenna matching network, a PCB
antenna and other passives, while providing access to all
GPIOs of the device.
❐
CY8CKIT-143,
PSoC 4 BLE 256KB Module, features a PSoC
4 BLE 256KB device, two crystals for the antenna matching
network, a PCB antenna and other passives, while providing
access to all GPIOs of the device.
❐
The
MiniProg3
device provides an interface for flash pro-
gramming and debug.
❐
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents
1
2
3
5
4
Document Number: 002-23053 Rev. **
Page 2 of 49
PSoC
®
4: 4200_BLE
Family Datasheet
Contents
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
BLE Radio and Subsystem ......................................... 6
Analog Blocks.............................................................. 7
Programmable Digital.................................................. 8
Fixed-Function Digital.................................................. 9
GPIO ........................................................................... 9
Special-Function Peripherals .................................... 10
Pinouts ............................................................................ 11
Power............................................................................... 16
Development Support .................................................... 17
Documentation .......................................................... 17
Online ........................................................................ 17
Tools.......................................................................... 17
Electrical Specifications ................................................ 18
Absolute Maximum Ratings ...................................... 18
Device-Level Specifications ...................................... 18
Analog Peripherals .................................................... 23
Digital Peripherals ..................................................... 27
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Ordering Code Definitions .........................................
Packaging........................................................................
WLCSP Compatibility ................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
29
30
37
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Document Number: 002-23053 Rev. **
Page 3 of 49
PSoC
®
4: 4200_BLE
Family Datasheet
Figure 2. Block Diagram
CPU Subsystem
PSoC
4200
32-bit
AHB-Lite
SWD/TC
SPCIF
Cortex
M0
48 MHz
FAST MUL
NVIC, IRQMUX
FLASH
Up to 256 KB
Read Accelerator
SRAM
Up to 32 KB
SRAM Controller
ROM
8 KB
ROM Controller
DataWire/
DMA
Initiator/MMIO
System Resources
Power
Sleep Control
WIC
POR
LVD
REF
BOD
PWRSYS
NVLatches
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Multi Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
Programmable
Analog
Programmable
Digital
4x TCPWM
CapSense
UDB
...
UDB
2x SCB
-I2C/SPI/UART
IOSS GPIO
(7x ports)
LCD
SAR ADC
(12-bit)
2x LP Comparator
Bluetooth Low
Energy Subsystem
BLE Baseband
Peripheral
1KB SRAM
GFSK Modem
24MHz XO
Reset
Reset Control
XRES
Test
Digital DFT
Analog DFT
x1
x4
SARMUX
CTBm
x2
2x OpAmp
Port Interface & Digital System Interconnect (DSI)
2.4 GHz
GFSK
Radio
32kHz XO
I/O: Antenna/Power/Crystal
High Speed I/O Matrix
Power Modes
Active/Sleep
DeepSleep
Hibernate
36x GPIOs, 2x GPIO_OVT
IO Subsystem
The PSoC 4200_BL devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The Arm SWD interface supports all programming and debug
features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debugging.
The PSoC Creator IDE provides fully integrated programming
and debugging support for the PSoC 4200_BL devices. The
SWD interface is fully compatible with industry-standard
third-party tools. With the ability to disable debug features, very
robust flash protection, and allowing customer-proprietary
functionality to be implemented in on-chip programmable blocks,
the PSoC 4200_BL family provides a level of security not
possible with multi-chip application solutions or with microcon-
trollers.
Debug circuits are enabled by default and can only be disabled
in firmware. If not enabled, the only way to re-enable them is to
erase the entire device, clear flash protection, and reprogram the
device with the new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test inter-
faces are disabled when maximum device security is enabled,
PSoC 4200_BL with device security enabled may not be
returned for failure analysis. This is a trade-off the
PSoC 4200_BL allows the customer to make.
Document Number: 002-23053 Rev. **
LDO
Page 4 of 49
PSoC
®
4: 4200_BLE
Family Datasheet
PSoC 4200_BL operates with a single external supply (1.71 to
5.5 V without radio, and 1.9 V to 5.5 V with radio). The device
has five different power modes; transitions between these modes
are managed by the power system. PSoC 4200_BL provides
Sleep, Deep Sleep, Hibernate, and Stop low-power modes. Refer
to the
Technical Reference Manual
for more details.
Clock System
The PSoC 4200_BL clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that no metastable conditions occur.
The clock system for PSoC 4200_BL consists of the internal
main oscillator (IMO), the internal low-speed oscillator (ILO), the
24-MHz external crystal oscillator (ECO) and the 32-kHz watch
crystal oscillator (WCO). In addition, an external clock may be
supplied from a pin.
IMO Clock Source
The IMO is the primary source of internal clocking in
PSoC 4200_BL. It is trimmed during testing to achieve the
specified accuracy. Trim values are stored in nonvolatile latches
(NVL). Additional trim settings from flash can be used to
compensate for changes. The IMO default frequency is 24 MHz
and it can be adjusted between 3 to 48 MHz in steps of 1 MHz.
The IMO tolerance with Cypress-provided calibration settings is
±2%.
ILO Clock Source
The ILO is a very low-power oscillator, which is primarily used to
generate clocks for the peripheral operation in the Deep Sleep
mode. ILO-driven counters can be calibrated to the IMO to
improve accuracy. Cypress provides a software component,
which does the calibration.
External Crystal Oscillator (ECO)
The ECO is used as the active clock for the BLE subsystem to
meet the ±50-ppm clock accuracy of the Bluetooth 4.2
Specification. PSoC 4200_BL includes a tunable load capacitor
to tune the crystal clock frequency by measuring the actual clock
frequency. The high-accuracy ECO clock can also be used as a
system clock.
Watch Crystal Oscillator (WCO)
The WCO is used as the sleep clock for the BLE subsystem to
meet the ±500-ppm clock accuracy for the Bluetooth 4.2
Specification. The sleep clock provides an accurate sleep timing
and enables wakeup at the specified advertisement and
connection intervals. The WCO output can be used to realize the
real-time clock (RTC) function in firmware.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO or from the WCO; this allows the watchdog operation
during Deep Sleep and generates a watchdog reset if not
serviced before the timeout occurs. The watchdog reset is
recorded in the Reset Cause register. With the WCO and
firmware, an accurate real-time clock (within the bounds of the
32-kHz crystal accuracy) can be realized.
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in PSoC 4200_BL is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to
higher-performance processors such as Cortex-M3 and M4. The
Cypress implementation includes a hardware multiplier that
provides a 32-bit result in one cycle. It includes a nested vectored
interrupt controller (NVIC) block with 32 interrupt inputs and a
wakeup interrupt controller (WIC). The WIC can wake the
processor up from the Deep Sleep mode, allowing power to the
main processor to be switched off when the chip is in the Deep
Sleep mode. The Cortex-M0 CPU provides a nonmaskable
interrupt (NMI) input, which is made available to the user when
it is not in use for system functions requested by the user.
The CPU also includes an SWD interface, which is a 2-wire form
of JTAG; the debug configuration used for PSoC 4200_BL has
four break-point (address) comparators and two watchpoint
(data) comparators.
Flash
The PSoC 4200_BL device has a flash module with 256 KB of
flash memory, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS
access time at 24 MHz. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required. Maximum erase and program time is 20 ms per row
(256 bytes). This also applies to the emulated EEPROM.
SRAM
SRAM memory is retained during Hibernate.
SROM
The 8-KB supervisory ROM contains a library of executable
functions for flash programming. These functions are accessed
through supervisory calls (SVC) and enable in-system
programming of the flash memory.
DMA
A DMA engine, with eight channels, is provided that can do 32-bit
transfers and has chainable ping-pong descriptors.
System Resources
Power System
The power system is described in detail in the section
Power on
page 16.
It provides an assurance that the voltage levels are as
required for the respective modes, and can either delay the mode
entry (on power-on reset (POR), for example) until voltage levels
are as required or generate resets (brownout detect (BOD)) or
interrupts when the power supply reaches a particular program-
mable level between 1.8 and 4.5 V (low voltage detect (LVD)).
Document Number: 002-23053 Rev. **
Page 5 of 49
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