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74V1G70STR

Description
Buffers u0026 Line Drivers Single Buffer
Categorylogic    logic   
File Size111KB,9 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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74V1G70STR Overview

Buffers u0026 Line Drivers Single Buffer

74V1G70STR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeSOT-23
package instructionLSSOP, TSOP5/6,.11,37
Contacts5
Reach Compliance Codecompliant
Factory Lead Time25 weeks 5 days
series74V
JESD-30 codeR-PDSO-G5
JESD-609 codee3
length2.9 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUFFER
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of functions1
Number of entries1
Number of terminals5
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeLSSOP
Encapsulate equivalent codeTSOP5/6,.11,37
Package shapeRECTANGULAR
Package formSMALL OUTLINE, LOW PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply2/5.5 V
Prop。Delay @ Nom-Sup10 ns
propagation delay (tpd)10 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.45 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.95 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width1.625 mm
74V1G70
SINGLE BUFFER
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 3.6ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUT
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
SOT23-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
DESCRIPTION
The 74V1G70 is an advanced high-speed CMOS
SINGLE BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
bs
O
PIN CONNECTION AND IEC LOGIC SYMBOLS
et
l
o
ro
P
e
uc
d
s)
t(
O
-
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
the supply voltage. This device can be used to
interface 5V to 3V.
so
b
te
le
ro
P
uc
d
SOT323-5L
s)
t(
T&R
74V1G70STR
74V1G70CTR
April 2004
1/9

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