Eice DR IV ER ™ Co m pac t
High voltage gate driver IC
2E DL fa mi ly
600 V half bridge gate drive IC
2EDL23I06PJ
2EDL23N06PJ
EiceDRIVER™ Compact
Final dat a s heet
<Revision 2.4>, 28.11.2017
Final
Indust rial Po wer C o ntrol
Edition 28.11.2017
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG
All Rights Reserved.
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EiceDRIVER™ Compact
2EDL family
Revision History
Page or Item
all
Subjects (major changes since previous revision)
change term VCC in VDD
<Revision 0.86>, 15.05.2014
<Revision 2.2>, 01.06.2016
Update maximum Ta from 95 C to 105 C in Table 5
<Revision 2.3>, 18.08.2016
p.2
p.3
p.15
Updated disclaimer
Updated Trademarks
Updated parameter
V
HO
o
o
p.21
Add Figure 15 Deadtime and interlock
<Revision 2.4>, 28.11.2017
p.15
th(j-top)
change to junction to top
Trademarks of Infineon Technologies AG
μHVIC™, μIPM™, μPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™,
CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™,
DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™,
eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™,
IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™,
ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™,
REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™,
TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.
Trademarks Update 2015-12-22
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Final datasheet
3
<Revision 2.4>, 28.11.2017
EiceDRIVER™ Compact
2EDL family
Table of Contents
1
2
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
4
4.1
4.2
4.3
4.4
4.5
4.6
5
6
6.1
Overview ............................................................................................................................................. 7
Blockdiagram...................................................................................................................................... 9
Pin configuration, description, and functionality ......................................................................... 10
Pin Configuration and Description...................................................................................................... 10
Low Side and High Side Control Pins (LIN, HIN) ............................................................................... 10
Input voltage range ............................................................................................................................ 10
Switching levels .................................................................................................................................. 10
Input filter time .................................................................................................................................... 11
VDD, GND and PGND (Low Side Supply) ......................................................................................... 11
VB and VS (High Side Supplies) ........................................................................................................ 11
LO and HO (Low and High Side Outputs) .......................................................................................... 11
Undervoltage lockout (UVLO) ............................................................................................................ 12
Bootstrap diode .................................................................................................................................. 12
Deadtime and interlock function ......................................................................................................... 12
EN-/FLT (fault indication and enable function) ................................................................................... 12
Power ground / over current protection .............................................................................................. 13
Electrical Parameters ....................................................................................................................... 14
Absolute Maximum Ratings ............................................................................................................... 14
Required operation conditions ........................................................................................................... 15
Operating Range ................................................................................................................................ 15
Static logic function table ................................................................................................................... 16
Static parameters ............................................................................................................................... 16
Dynamic parameters .......................................................................................................................... 18
Timing diagrams............................................................................................................................... 19
Package ............................................................................................................................................. 22
PG-DSO-14 ........................................................................................................................................ 22
Final datasheet
4
<Revision 2.4>, 28.11.2017
EiceDRIVER™ Compact
2EDL family
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Typical Application ............................................................................................................................... 8
Block diagram for 2EDL23x06PJ ......................................................................................................... 9
Pin Configuration of 2EDL family ....................................................................................................... 10
Input pin structure............................................................................................................................... 11
Input filter timing diagram ................................................................................................................... 11
EN-/FLT pin structures and interface to microcontroller (µC) ............................................................ 12
Timing of short pulse suppression ..................................................................................................... 19
Timing of of internal deadtime ............................................................................................................ 19
Enable delay time definition ............................................................................................................... 19
Input to output propagation delay times and switching times definition ............................................. 20
Operating areas (IGBT UVLO levels)................................................................................................. 20
Operating areas (MOSFET UVLO levels) .......................................................................................... 20
ITRIP-Timing ...................................................................................................................................... 21
Output pulse width timing and matching delay timing diagram for positive logic ............................... 21
Deadtime and interlock ...................................................................................................................... 21
Package drawing ................................................................................................................................ 22
PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint .... 22
Final datasheet
5
<Revision 2.4>, 28.11.2017
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