Simple design method tutorial Verilog quickly masters the new version

Ming Deyang's minimalist design method was pioneered by Pan Wenming, a teacher with many years of experience in writing FPGA codes. It not only allows beginners to master the Verilog language in a short time, but also produces simple and non-redundant codes with high accuracy. We will use a series of cases to provide you with efficient guidance on Verilog.

• Chapter 1：01 D trigger and code (8 minutes and 5 seconds)

• Chapter 2：02 FPGA design thinking (11 minutes and 36 seconds)

• Chapter 3：03 Our first design (19 minutes and 2 seconds)

• Chapter 4：04 Our first design idea (15 minutes and 3 seconds)

• Chapter 5：05 The first summary of design grammar (18 minutes and 22 seconds)

• Chapter 6：06 Our second design - serial port (2 minutes and 9 seconds)

• Chapter 7：07 Our second design - serial port idea (23 minutes and 54 seconds)