Altera FPGA design skills improvement training

Based on Altera FPGA and Quartus II development software, you can learn FPGA design skills and improve your FPGA design skills. Including the trade-off between area and speed, hardware implementation, hierarchical design and synchronous design, etc.

• Chapter 1：From schematic to HDL (31 minutes and 45 seconds)

• Chapter 2：Development and Prospects of FPGA (24 minutes and 33 seconds)

• Chapter 3：Design process of Verilog HDL module (43 minutes and 13 seconds)

• Chapter 4：Design a sixteen-bit adder (34 minutes and 49 seconds)

• Chapter 5：FPGA design principles and techniques (1): Tradeoff between area and speed (15 minutes and 39 seconds)

• Chapter 6：FPGA design principles and techniques (2): hardware implementation, hierarchical design and synchronization principles (21 minutes and 58 seconds)

• Chapter 7：Use of IP cores in FPGA (13 minutes and 17 seconds)

• Chapter 8：Three types of modeling in Verilog HDL: data flow modeling, behavioral modeling and structured modeling (54 minutes and 2 seconds)

• Chapter 9：Verilog code and Testbench preparation of D-type flip-flop (29 minutes and 41 seconds)

• Chapter 10：Exercise: BCD code encoder_stepwise shifting method (14 minutes and 21 seconds)

• Chapter 11：Basic elements, types and HDL-level implementation of state machines (44 minutes and 35 seconds)

• Chapter 12：One-stage state machine exercise (5 minutes and 27 seconds)

• Chapter 13：Implement the marquee experiment on Quartus II (28 minutes and 43 seconds)

• Chapter 14：Detailed explanation of 2-stage and 3-stage state machines and experiments in Qurtus II (35 minutes and 10 seconds)

• Chapter 15：The use of IP cores in FPGA and key points of HDL statements (53 minutes and 29 seconds)