Location:Training / Embedded Development / FPGA / Xilinx UltraScale Getting Started Tutorial / How to use Vivado MIG to design memory interfaces and controllers for UltraScale devices

Including Xilinx UltraScale SelectIO CTLE performance demonstration, how to use XPE tools to analyze the power consumption of UltraScale devices, UltraScale BRAM performance and power consumption advantage demonstration, UltraScale DSP and clock power consumption reduction function demonstration, how UltraScale reduces power consumption, and use System Monitor to monitor Operating environment, using the system management wizard for system monitoring design, how to use Vivado MIG to design memory interfaces and controllers for UltraScale devices, why ASIC-like clock technology and advantages are used in UltraScale, and how to create and use UltraScale PCIe design examples.