Location:Training / Embedded Development / Computer composition and design: RISC-V (Zhejiang University) / Address Translation Cache II

  This course is a professional basic course for information and electronic engineering and related computer majors. The course includes processor RISC-V instruction set, addressing mode, data types, assembly language, processor microstructure, controller and pipeline, storage system, cache , virtual storage, multi-processor and parallel technology, system design performance evaluation and software and hardware co-design methods, etc.

This course can be combined with offline teaching to provide students with an online platform for review, Q&A and self-evaluation, further consolidating and expanding the content learned in the classroom, and strengthening communication between students and teachers outside the classroom; it can also serve as a Online learning resources for undergraduates in information engineering and computer-related majors in colleges and universities to study courses such as "Computer Composition and Design" and "Computer System Structure"; and can be used as a reference for computer-related professionals and relevant teachers in colleges and universities.

This course is based on the interpretation and teaching of RISC-V instruction set architecture. While mastering the traditional computer composition knowledge, you can also learn to understand the instruction set and system architecture design methods.