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EC340egb timer

Overview

CMOS manufacturing process, low power consumption. Wide voltage range and strong anti-interference ability. OUT outputs low level, and the timing time range is wide, and the timing mode can be selected from 8-512 times the difference. When the timer is powered on, the high potential (high impedance state) is not reached. When the button is pressed, the timing starts, and OUT outputs a low level. When the timing time is up, the output changes to a high potential (high impedance state) and is invalid if triggered midway.
R time selection method:

KEY1=0, KEY2=0 are both left floating, the timing time is as shown in the table below

KEY1=VDD, KEY2=VDD and connect to VDD at the same time, the timing time is 512 times as shown in the table

KEY1=VDD, KEY2=0 timing time is 8 times as shown in the table

KEY1=0, KEY2=VDD timing time is 64 times as shown in the table

Design Files

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Update:2025-05-08 10:18:33

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