[Changshu Institute of Technology] Differential amplifier circuit tester

(1) Competition question requirements

(1) Build a triode differential amplifier circuit according to the circuit shown in the figure, and debug it to make it work normally. The transistor uses 9013.

Figure 2 Transistor differential amplifier circuit

(2) Design a differential signal source to test the performance of the produced amplifier and generate the differential signal uid used for testing. uid meets the following requirements:

        a) Common mode signal voltage range: 0V~1V, 10mV step.
        b) Differential mode signal voltage range: amplitude (0-100mV), 10mV step; frequency range 100Hz~1MHz, 100Hz step.
        c) uid common mode signal voltage and differential mode signal amplitude can be set, and the differential mode signal frequency can be set.

        d) The error between the uid parameter index displayed by the tester and the uid parameter index measured and observed by the oscilloscope shall not exceed 5mV.

(3) Measure the magnification and display the record. Measure the voltage amplification factor A of the amplifier at 1KHz.

(4) Input resistance measurement, measure the input resistance of the amplifier at 1KHz.

(5) Measure the amplitude-frequency characteristics of the differential amplifier circuit and display it on the LCD screen to calculate the upper limit cutoff frequency. 

(6) Others

(7) Design report

(2) Engineering principles

Signal generator principle

The principle of the signal generator is based on the relationship between the phase and amplitude of the cosine function . Starting from the phase , different voltage amplitudes are given by different phases , and then after D/A conversion and filtering, an analog signal of a certain frequency and frequency modulation is obtained. , Figure 2.1 The principle block diagram of the signal generator shows the functional modules of the signal generator.

Figure 3-1-1 Signal generator schematic diagram

If the phase accumulator has N bits , the clock frequency is c1ock, and the frequency control word is Fword . The N- bit phase accumulator can divide the clock frequency by 2N , so the accuracy of the signal generator reaches

 (2.1)

The frequency control word is used to control the step of the accumulator. The step calculation formula of the accumulator is                                                                                                                                   (2.2)       

                                                                                                                                                                      ( 2.3 )

                                                                                                                                            ( 2.4 )

The workflow of the signal generator is to sample and quantize the required DDS waveform . Then store the quantized data directly into the BlockRAM of the FPGA , and then read the data directly from the BlockRAM under the control of the clock frequency and send it to the DDS. /A then output the original waveform.

Differential amplifier principle

In a differential mode circuit, the equivalent input drift voltage of the two differential tubes caused by temperature changes and power supply fluctuations is equivalent to a pair of common mode signals, which greatly reduces the drift voltage of the output end of each tube. If the double-ended output, will be completely canceled, while the differential mode signal will be amplified normally.

Figure 4-1-2 Input waveform simulation

Figure 4-1-3 Output waveform simulation

(3) Test plan and test results

After field testing, two 1KHz sine wave differential mode signals with a peak-to-peak value of 0.05V are input, the amplification factor is about 48 times, and the common mode signal is suppressed.

Since the signal generator was not successfully manufactured, the input signal in the test session was the signal generated by the dual-channel signal generator, so the amplitude-frequency curve was not completed.