【Development Board】ESP32-CAM-12K (S2 and S3)

The ESP32-CAM development board with Essence ESP32-12K/ESP32-S3-12K as the core has an additional 10 pins.

The power ground wire and serial port pin positions are compatible with ESP32-CAM. It is equipped with ESP32-S3-12K module and is connected to OV2640 camera, which can exceed 25fps at 1024*768 resolution.

You can attach 12K (S2 chip) or S3-12K (S3 chip). It is recommended to attach S3-12K. The corresponding relationship is marked in the pin schematic diagram of the two modules. The PCB silk screen pins are marked as 12K (S2 chip) module pins.

If you attach a 12K module, please refer to the camera pin definition.
#define PWDN_GPIO_NUM    14
#define RESET_GPIO_NUM   21
#define XCLK_GPIO_NUM    15
#define SIOD_GPIO_NUM    4
#define SIOC_GPIO_NUM    5

#define Y9_GPIO_NUM      16
#define Y8_GPIO_NUM      17
#define Y7_GPIO_NUM      18
#define Y6_GPIO_NUM      12
#define Y5_GPIO_NUM      10
#define Y4_GPIO_NUM      8
#define Y3_GPIO_NUM      9
#define Y2_GPIO_NUM      11
#define VSYNC_GPIO_NUM   6
#define HREF_GPIO_NUM    7
#define PCLK_GPIO_NUM    13

If S3-12K module is attached, camera reference pin definition:

#define PWDN_GPIO_NUM    2
#define RESET_GPIO_NUM   21
#define XCLK_GPIO_NUM    38
#define SIOD_GPIO_NUM    4
#define SIOC_GPIO_NUM    11

#define Y9_GPIO_NUM      39
#define Y8_GPIO_NUM      17
#define Y7_GPIO_NUM      18
#define Y6_GPIO_NUM      12
#define Y5_GPIO_NUM      10
#define Y4_GPIO_NUM      8
#define Y3_GPIO_NUM      5
#define Y2_GPIO_NUM      6
#define VSYNC_GPIO_NUM   13
#define HREF_GPIO_NUM    14
#define PCLK_GPIO_NUM    7

Note:

Essence has discontinued the ESP32 module. I have reproduced an S3-12K module for reference: https://oshwhub.com/njbinbin/esp32-s3-12k-clone_copy , but it is not recommended to be used with the official product. Its pins It is not fully compatible with the original 12K. If the OTG pin connected to this development board is used as a DVP camera and is therefore unavailable, the silk screen pin markings on the development board will no longer apply. The pin correspondence is as follows:

GND VCC 00 01 09 03 04 11 13 14 08 05 10 06 12 07 02 38 39 17 18 19 20 21 48 GND 33 34 35 36 37 15 16 40 41 42 TX RX 45 46 EN GND

GND VCC 00 03 05 07 09 06 10 08 11 12 13 14 15 16 17 18 19 20 21 48 34 36 33 GND 35 37 38 39 40 04 41 42 45 46 TX RX 02 01 EN GND

Corresponding pin definition (OTG pins 19 and 20 are used):

#define PWDN_GPIO_NUM    17
#define RESET_GPIO_NUM   36
#define XCLK_GPIO_NUM    18
#define SIOD_GPIO_NUM    9
#define SIOC_GPIO_NUM    6

#define Y9_GPIO_NUM      19
#define Y8_GPIO_NUM      20
#define Y7_GPIO_NUM      21
#define Y6_GPIO_NUM      15
#define Y5_GPIO_NUM      13
#define Y4_GPIO_NUM      11
#define Y3_GPIO_NUM      12
#define Y2_GPIO_NUM      14
#define VSYNC_GPIO_NUM   10
#define HREF_GPIO_NUM    8
#define PCLK_GPIO_NUM    16

renew:

A special PCB has been added for attaching the replica S3-12K module, and the OTG pins have been adjusted. The pin definitions are as follows:

#define PWDN_GPIO_NUM    17

#define RESET_GPIO_NUM   36

#define XCLK_GPIO_NUM    18

#define SIOD_GPIO_NUM    9

#define SIOC_GPIO_NUM    6

#define Y9_GPIO_NUM      21
#define Y8_GPIO_NUM      48
#define Y7_GPIO_NUM      34
#define Y6_GPIO_NUM      15

#define Y5_GPIO_NUM      13

#define Y4_GPIO_NUM      11

#define Y3_GPIO_NUM      12

#define Y2_GPIO_NUM      14

#define VSYNC_GPIO_NUM   10

#define HREF_GPIO_NUM    8

#define PCLK_GPIO_NUM    16