PCIe_Bifurcation

To split the 16 PCIEX16 lanes of the computer motherboard into four 4-lane lanes, the motherboard needs to support PCIE splitting.

Each channel enjoys full speed of X4 (whether it is PCI-E 3.0 or PCI-E 4.0 depends on your motherboard).

The PCIE clock uses Texas Instruments' LMK00334RTVR clock cache chip. The Buffer has four channels for four SSDs. (Currently, ICS and PIC clock cache chips are out of stock and high prices. Lichuang Mall has this TI chip. The wiring and resistor usage of this chip are relatively strict. )

Each M.2 SSD interface is powered by Texas Instruments' TPS54620RHLR all-in-one BUCK chip to provide a maximum current output of 3.3V 6A for each port (because it is a test, I used TI's, which is still relatively expensive. Students who copy homework can Replace it with a cheap one, or even a foreign junk module like PW22A) to meet the needs of high-power M.2 SSD.

And the reset signal with PG signal and PCIE provides an independent reset signal to each M.2 port through a single dual-input positive AND gate. It adopts PCIE full-length and full-height design and supports four 22110 length M2 SSDs.

The TYPEB at the back is connected to the USB3.1/USB3.0 interface of the motherboard. The bezel supports one 10G TYPEC and one 10G TYPEA. There is one 10G TYPEA and one USB2 reserved interface on the board. (The original plan was to speed up the charging of the chip, but it was out of stock, so the C port only supports 5V 3A at most. Because there is no reversible PD MUX chip, the C port occupies 2 USB3.1 channels)

Continuous update log:

2022/7/8 Project establishment

The basic layout was completed on 2022/7/11 and wiring is continuing. . . .

2022/7/14 The project has been basically completed and is waiting for physical verification by Lichuang

2022/7/28 Jialichuang board arrives

After the board arrives, measure the resistance and voltage first to prevent BOOM.

There is no obvious problem with the resistance value when testing the voltage. When testing the voltage, it was found that the 5V voltage of the USB is only 2.4V, and the 3.3V of the four M.2s is normal. Looking at the schematic diagram, it is found that the DC FB voltage dividing resistors for 5V step-down are 20K and 10K, which should be 52.3 K and 10K, after replacing the resistor, the 5V output is normal, and the schematic and PCB have been corrected.

If you install the old yellow fan of Faith, it will be full of power.

Compared with the graphics card, the length is the same

How it looks like with the M.2 SSD installed and ready to be put on the computer. God bless me not to explode.

2022/7/29: After testing on the computer, it was found that only two PM983A were recognized, and PM963 was not recognized. Change other SSDs, some are recognized, and some are not recognized. Change the SSD, and PM983A is recognized no matter where it goes. Test PERST, and the battery Normal. I can only doubt the clock. I checked the LMK00334 specification and found that the 100Ω impedance of the clock differential line requires a 33R resistor and a 49.9 pull-down resistor. I used the correct resistors, but my differential impedance lines are all drawn with 85 ohms, which is different from the resistor value. It matches, and the specification says that the pull-down resistor should be placed next to the series resistor, so I drilled a hole and placed it behind. After I replaced the 27.4R series resistor and 42.2R pull-down resistor, they all worked. (The schematic and PCB have been corrected to 100OHM clock differential lines)

2022/8/4: Because I have been ill recently, I put it on hold. After solving the SSD problem, I will test the USB.

There was no problem with USB. After connecting TYPEB to the motherboard, it was a success.

Problems with most people’s relationships:

Question: Why does this board need to add USB?

Answer: Originally, my plan was to provide TYPEC fast charging and provide data support, but I found that fast charging chips are difficult to buy. I have already drawn the USB HUB picture, so I did not delete it. I just want to make a VIA HUB reference design for everyone.

Question: Why is there still a USB in the board?

Answer: Because it is envisaged that a display screen will be added to the casing to display the capacity and temperature of the four SSDs in real time. However, it feels too gaudy. For your reference, you can remove this USB HUB.

Question: Don’t I need to connect PCI-E WAKE, SMDATA, and SMCLK?

Answer: PCI-E only has three data functions: PERST, REFCLK+-, data TX+- and RX+-. Everything else is optional. You can use whichever power supply you want. External power supply is also acceptable. SMBUS is just an I2C signal, not mandatory, and the M.2 SMBUS has a 1.8V pull-up and cannot directly activate PCI-E SMBUS. As for WAKE, this is PCIE wake-up and is not needed for SSD. Only network cards are used. Even if the network card is not connected to WAKE#, it can be used normally, but it cannot wake up the host through the network card. WAKE# needs to work with 3.3VAUX. So if your network card is connected to WAKE#, for example, you need to provide the network card with a standby voltage.

Question: Is the PCI-E impedance 100 or 85?

Answer: 100 and 85 have no effect. You can draw either 100 or 85. PCIE is more interested in impedance uniformity.

Regarding REFCLK, because the standard PCI-E socket has only one pair of clocks, after you split it, it becomes multiple PCIE devices. Each PCI-E device requires a pair of clocks, so you need a chip to switch the clocks to multiple to the clock.

Regarding PERST, why do I use dual input main entrance here. PERST is a reset signal. When the PCIE device is running normally, it is at a high level of 3.3V (it sounds like a PG signal, but it is actually about the same), but there is a delay after PERST is powered on (you seem to have heard it in the ATX PG signal) . Multiple PCIE PESRTs can be directly short-circuited and used together, but in this way, they will all be reset once reset. Adding a dual-input front gate allows the PG signal through the DC step-down chip to be used with PERST to reset each PCIE device individually. In fact, you can just connect these PERSTs in parallel without considering plugging and unplugging them under power.

About the USBOC and USBPE pins of VIA USB3 HUB. USBPE is an output. When the chip diagnoses that a device is inserted into this interface, USBPE will become high level. USBOC is an input. If a high level is input, the USB port will work normally. If a low level is input, the port will stop. USBOC and USBPE are used for the load detection switch chip of each port. If you don’t want to add this retest switch chip (these are low internal resistance NMOS, usually not cheap, many people just add a resettable fuse), USBOC must be pulled high, USBOC must be pulled high, USBOC must be To pull higher. I see that many HUB works in summer camps are left blank, and then the response is that they cannot be used, of course they cannot be used.

You can leave USBPE blank, or you can connect any LED to the series resistor.

The most critical:

The PCIE differential pair supports polarity reversal (in human terms, the PCIE differential data does not distinguish between +- and PN. You can reverse it, including the clock differential pair. This is not a function of the HOST end, but a function of each PCI-E device. In implementation, is a mandatory function),

The PCIE data differential pair supports overall channel flipping (that is, 0, 1, 2, 3 on your motherboard can be used to flip 3, 2, 1, 0 on the device side. Note that it is an overall flip, either you don’t flip it, or all flips are not supported. Single flip, mixed flip is not supported. After you split PCIE, each segment is independent. Flip is supported in each segment.)

The overall flipping and polarity flipping of the PCIE data differential channel can exist at the same time! Transceiver flipping is not supported, transceiver flipping is not supported, transceiver flipping is not supported!

USB3.0/USB3.1/USB3.2 differential pairs support polarity flip! (Excluding the USB2.0 data pair inside), transceiver flipping is not supported, transceiver flipping is not supported, transceiver flipping is not supported, transceiver flipping is not supported!

Displayport differential pairs do not support polarity flipping and channel flipping! Nothing is supported!