A4950 dual-channel motor driver board

#### Chip Introduction
The A4950 is designed to run DC motors. The output drivers are all low RDS(on), N-channel DMOS drivers with internal synchronous rectification to reduce power consumption. The current in the output full bridge is regulated by a fixed off-time pulse width modulation (PWM) control circuit. The IN1 and IN2 inputs allow two-wire control of the bridge. Protection circuits include internal thermal shutdown, short-circuit load protection, and output short-circuit protection to ground or power supply. Undervoltage lockout prevents damage by keeping the output off until the driver has enough voltage to operate normally.
#### Chip features
1. Overcurrent protection, motor short-circuit protection, low standby current, PWM speed regulation
2. Maximum output current 3.5A, maximum voltage 40V
3. VBB: load supply voltage, 8~40V
4. Vref: 0.3~6V
5. Vs: detection voltage (LSS7 pin), -0.5~0.5V
#### PWM control truth table
|INA1|IN2|10*Vs > Vref|OUT1|OUT2|Function|
|---|---|---|---|---|---|
|0|1|False|L|H|Reverse|
|1|0|False|H|L|Forward|
|1|1|False|L|L|Braking, slow decay|
|0|0|False|High impedance|High impedance|Inertia operation, enter low power standby mode after 1 ms|
|0|1|True|H/L|L|PWM speed regulation, reverse|
|1|0|True|L|H/L|PWM speed regulation, forward|
#### Current limiting resistor setting
$Imax = frac{Vrf}{10*Rs}$
For example, Vref=5V,Rs=0.16Ω, then Imax=3.125A
Vref = 3.3V, Rs = 0.1Ω, then Imax=3.3A