The software part of this tool (including the host computer) is not open source, but the schematic diagram and PCB related files are.
The design is a custom 3d model from Sensirion. Sensirion provides a 3d model, but it has very few features.
SYZYGY is an FPGA extension standard for medium to high speed interfaces. This breakout connects the SerDes in the SYZYGY-TXR connector to the card edge to act as a PCIe x4 add-in card. This breakout is very simple and can be made into a shorter SYZYGY pod.
The MAXREFDES62# reference design ushers in the era of Industry 4.0. With dual RS-485 communication channels for the next generation of ultra-small programmable logic controllers, this design meets the data rate and higher voltage needs of industrial control and industrial automation applications, while consuming minimal power and space. This high-performance system features one half-duplex RS-485 transceiver, one full-duplex RS-485 transceiver, a complete, efficient power-supply system and on-board processing. Hardware and firmware design files as well as results of lab measurements are provided.
This design is a PMOD with the ublox NEO GNSS receiver footprint. Able to receive GPS and GLONASS simultaneously.
EXPLORE-NFC - exclusively supplied by element14
This design has a PMOD for the SD card to emulate the SD card to the host system.
In early 2005, NEC Electronics launched small-pin-count microcontrollers such as PIC/AVR based on the 78K0S architecture. The 78K architecture has a register set similar to the i8085 and additional bit manipulation instructions. It is said to be a classic architecture, but the memory organization is simpler than PIC/AVR. There are various devices with dedicated peripherals, and the 78K series occupies a considerable share of industrial equipment. In the early days, only OTP/Mask products were available, so they were not popular among electronic crafts. However, the small pin count 78K series with flash memory is getting some attention from Japanese microcontroller geeks. Powerful IDEs (compilers, assemblers, simulators, etc.) are also provided for free. I built a very simple 78K0S flash programming adapter for these devices. Additionally, I built a universal programming adapter for V850ES, LPCxxxx, STM32F, etc.
The SA636DK evaluation demonstration board is used to evaluate the RF development platform for 110.592 MHz RF and 9.8 MHz IF.
Core64 combines real core memory and LEDs in a unique interactive way. Core Memory is a magnetic memory technology from the 1960s and 1970s. The tip of the stylus has a magnet that interacts with the LED through Core Memory. In practice, users can think of it as a magnetic touch screen
This board and associated firmware can be used to switch between two serial NMEA GPS feeds based on repair status. The resulting feed is transmitted over a third serial line with RS232 levels. This board is designed around the Cypress PSoC CY8C27143. The PCB is designed using KiCAD.
Use ESP32S3 to develop a general module with speech recognition and visual recognition functions. It is mainly used for education, science and technology competitions, and creative design of DIY enthusiasts. The interface and functions are compatible with OpenMV, and its IDE can be used as development and debugging software. Most of the overall hardware design is compatible with ESP32S-EYE, so with a little adjustment of the interface definition, it can be compatible with ESP-WHO. ESP-WHO provides examples such as face detection, face recognition, cat face detection and gesture recognition, thus making this software The module is very playable.
A PMOD with a quad 7-segment display connected to a pair of 74hc595 shift registers. There are 3 tactile buttons.
Single-Pair-Ethernet technology (SPE, Single-Pair-Ethernet) describes the transmission of Ethernet through only a pair of copper cores. In addition to transmitting data through Ethernet, it can also simultaneously provide power to terminal devices through PoDL (power supply over data lines).
The Sonoma (MAXREFDES14#) subsystem reference design performs accurate AC energy measurement while utilizing a unique, low-cost galvanic isolation architecture. The Sonoma meets the high-accuracy and low-cost needs of energy-measurement applications. This small form-factor design is available for purchase. Hardware, firmware design files, and lab measurements provide complete system information for rapid prototyping and development.
This reference design (RD) is for a dual-band, triple-mode front-end IC using only 85MHz IF centers for processing PCS, cellular CDMA, and cellular AMPS. The RD uses the MAX2323, a low-noise amplifier (LNA) with mixer, that is useful for TDMA, GSM, EDGE, and WCDMA applications.
This reference design (RD) for an RF mixer in the FM (AMPS) signal path custom tunes the output matching circuit to optimize the trade-off between IIP3 and the highest gain. The design features the MAX2324 low-noise amplifier (LNA) with RF mixer for cellular-band CDMA, TDMA, GMS, and EDGE applications.
The RSL10 module is plugged into the self-made optocoupler isolation circuit board, and the entire module is connected in series with the modified target instrument (4-20mA two-wire passive digital display meter) and then connected to the 4- In the 20mA current loop, when the actual working zero current is 4mA, the target instrument displays 4.000mA in the current mode; the overall voltage drop of the circuit board of the work is 2.513V; the changed range or unit is sent to the RSL10 on the circuit of the work through the mobile APP Setting command, the target instrument (currently its own voltage drops by more than 1V) will be changed by Bluetooth remote control to change the setting state, such as switching to different ranges or displaying different measured physical quantity units, etc.