Problems with using multiple PLLs

zhenpeng25

Problems with using multiple PLLs [Copy link]

I first used a PLL frequency division, and then connected a clock selection module, as shown in the figure. Later, I want to continue to divide the selected clock. Can I still use PLL frequency division? I tried to compile it but it didn't pass. Has anyone done something similar? Please advise.

枫叶知秋

OK, why doesn't it compile? What went wrong?

wangzhf1990

What does it mean if the compilation fails?

过客2011

Can it run over 200M?

kdy

Yes

dell_wang

I can implement IP frequency division in Xlinx. It seems that I need to check the next option of IP core design below.

zhenpeng25

kdy posted on 2014-2-17 17:45 Yes

I want to connect it this way, but the compilation fails. Please advise. The error is: Error: Clock input port inclk[0] of PLL "pll1:inst12|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Info: Input port INCLK[0] of node "pll1:inst12|altpll:altpll_component|pll" is driven by clkopt:inst9|Mux0 which is COMBOUT output port of Combinational cell type node clkopt:inst9|Mux0

zhenpeng25

Posted by Fengye Zhiqiu on 2014-1-14 16:46 OK, why doesn't the compilation pass? What's the error?

I want to connect like this, but the compilation fails. Please give me some advice. The error is: Error: Clock input port inclk[0] of PLL "pll1:inst12|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Info: Input port INCLK[0] of node "pll1:inst12|altpll:altpll_component|pll" is driven by clkopt:inst9|Mux0 which is COMBOUT output port of Combinational cell type node clkopt:inst9|Mux0

zhenpeng25

wangzhf1990 posted on 2014-1-27 13:02 What is the prompt when the compilation fails?

I want to connect like this, but the compilation fails. Please give me some advice. The error is: Error: Clock input port inclk[0] of PLL "pll1:inst12|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Info: Input port INCLK[0] of node "pll1:inst12|altpll:altpll_component|pll" is driven by clkopt:inst9|Mux0 which is COMBOUT output port of Combinational cell type node clkopt:inst9|Mux0

kdy

This hint means that the inclk[0] pin must be driven by a specific pin.

zhouganqiu

zhenpeng25 posted on 2014-2-26 19:55 I want to connect it this way, but the compilation fails. Please advise. The error is: Error: Clock input port inclk[0] of PLL "pll1:inst ...

The input clock of PLL must be connected from a specific chip pin and cannot be connected from the output of the internal logic. The PLL series connection can be achieved by outputting the clock to be divided from a pin and then inputting it from the specific clock input pin of the PLL.

641734667

How do you solve this problem? :time:

sgphoto

Learned. The second PLL, if it is not a fractional frequency division, can use logic units to complete the frequency division.

jp652rubyxg

zhouganqiu posted on 2014-3-13 11:14 The input clock of PLL must be connected from a specific chip pin, and cannot be connected from the output of internal logic. Output the clock to be divided from a pin...

I don't quite understand what you mean. Can you give an example? I have the same problem now...

jp652rubyxg

sgphoto posted on 2016-4-12 16:32 I have learned that if the second PLL is not a fractional frequency division, the logic unit can be used to complete the frequency division.

How to complete the frequency division with the logic unit?

jp652rubyxg

https://www.altera.com/support/s ... rd02012010_744.html What does this ALTERA description mean? How can I solve the problem? I don't understand