No timing issues encountered

gaorz_

No timing issues encountered [Copy link]

SPI's CPOL=0, CPHA=1, falling edge data is written from the controller to the chip, and rising edge data is read from the chip to the controller. The falling edge of the first clock writes the MSB of the data, and the rising edge (the second rising edge) reads the MSB of the data. The last falling edge writes the LSB of the data, so is there a lack of a rising edge to read the LSB of the data?