[Xiao Meige FPGA Advanced Tutorial] Chapter 5 Passive Buzzer Driver Design
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Passive buzzer driver design Buzzer is an electronic sounder with an integrated structure. It is powered by DC voltage and is widely used as a sound-generating device in electronic products such as computers, printers, copiers, alarms, electronic toys, automotive electronic equipment, telephones, timers, etc. Buzzers are mainly divided into two types: piezoelectric buzzers and electromagnetic buzzers. Piezoelectric buzzer: Piezoelectric buzzer is mainly composed of multivibrator, piezoelectric buzzer, impedance matcher, resonance box, shell, etc. Some piezoelectric buzzers are also equipped with light-emitting diodes on the shell. Multivibrator is composed of transistors or integrated circuits. When the power is turned on (1.5~15V DC working voltage), the multivibrator starts to oscillate and outputs an audio signal of 1.5~2.5kHZ. The impedance matcher drives the piezoelectric buzzer to make a sound. Electromagnetic buzzer: The electromagnetic buzzer consists of an oscillator, an electromagnetic coil, a magnet, a vibrating diaphragm and a shell. After the power is turned on, the audio signal current generated by the oscillator passes through the electromagnetic coil, causing the electromagnetic coil to generate a magnetic field. Under the interaction between the electromagnetic coil and the magnet, the vibrating diaphragm vibrates periodically and makes a sound. Depending on whether the buzzer itself integrates an oscillation source, the buzzer can be divided into an active buzzer and a passive buzzer. An active buzzer can make a continuous sound by directly connecting it to the rated power supply (new buzzers are marked on the label); while a passive buzzer, like an electromagnetic speaker, needs to be connected to the audio output circuit to make a sound. The difference between active buzzer and passive buzzer: Note: The "source" here does not refer to the power supply, but to the oscillation source. That is to say, the active buzzer has an oscillation source inside, so it will buzz as long as it is powered on; The passive buzzer does not have an oscillation source inside, so it cannot be made to buzz if a DC signal is used. It must be driven by a 2K-5K square wave Active buzzers are often more expensive than passive ones because there are multiple oscillation circuits inside. The advantages of passive buzzers are: 1. Cheap 2. The sound frequency is controllable, and the effect of "Doremifasolasi" can be produced 3. In some special cases, it can reuse a control port with LED The advantages of active buzzers are: easy program control. The above introduces the types of buzzers and the characteristics of active buzzers and passive buzzers. Next, we will introduce the buzzer circuit used on the mainboard of the Core Line FPGA Learning Kit, and use Verilog to design a buzzer driver circuit to drive the buzzer to sound. Introduction to Buzzer CircuitA 3.3V driven passive buzzer is used on the mainboard of the Core Line FPGA Learning Kit. Its circuit is shown below: Capacitor C37 is used to improve the anti-interference performance of the circuit. D1 plays the role of protecting the transistor. When the transistor is suddenly cut off, the instantaneous induced electromotive force generated at both ends of the passive buzzer can be quickly released through D3 to avoid being superimposed on the collector of the transistor and thus breaking down the transistor. The beep port is connected to the FPGA output pin. When in use, you only need to output a 2~5KHz PWM wave on the beep signal to drive the buzzer to sound. Passive buzzer controller design From the previous introduction to the characteristics of the passive buzzer, it can be known that in order for the passive buzzer to sound normally, it is necessary to give a PWM wave of the corresponding frequency at the control end beep. Therefore, the control of the passive buzzer is transformed into designing a PWM wave generation circuit. Therefore, next we will introduce the design of the PWM wave generation circuit. What is PWM wave? The full name of PWM in English is Pulse Width Modulation, which is pulse width modulation. By modulating the width of a series of pulses, the required waveform (including shape and amplitude) is equivalently obtained. PWM control technology is most widely used in inverter circuits. Most of the inverter circuits used are PWM type, which are widely used in many fields from measurement, communication to power control and conversion. The following are the periods of 1KHz, and the pulse widths (duty cycles) are 20%, 50% and 100% respectively.serif]90%waveform:
It can be seen from the figure that when the signal cycle is constant, the percentage of the signal high level time in the total time is different, that is, the PWM wave with different duty cycles. In the inverter circuit, when such a waveform is used to drive the conduction of the MOS tube, because the high level duration of the PWM signal with different duty cycles in one cycle is different, the opening time of the MOS tube is also different, so the average current in the circuit is also different. Therefore, the average current in the controlled circuit can be adjusted by adjusting the duty cycle of the driving signal. In addition to adjusting the duty cycle of the PWM signal, the period of the PWM signal can also be adjusted. For example, in the inverter circuit, IGBT is used as a switching device, and the common switching frequency is several K to tens of K, while the switching frequency of MOS tubes can be as high as hundreds of K. Therefore, for different devices, the frequency requirements of the drive signal are also different. Therefore, it is also necessary to be able to adjust the frequency of the PWM wave. Through the above analysis, it can be known that to design a PWM generation circuit, it is necessary to be able to adjust the frequency and duty cycle of the signal. Friends who have used a single-chip microcomputer or DSP to generate PWM waves should know that in a single-chip microcomputer or DSP, the method of generating PWM waves is to use an on-chip timer for cyclic counting, and determine the frequency of the corresponding output PWM signal by setting a timing cycle of the timer. At the same time, there is a comparator, which compares the real-time count value of the timer with the comparison value set by the user, and controls the level of the output signal according to the comparison result. By setting different comparison values, PWM signal outputs with different duty cycles can be achieved. For FPGA, to generate PWM wave, we can also learn from the idea of using timer to generate PWM wave by microcontroller or DSP. PWM circuit design based on FPGAAccording to the typical principle of DSP generating PWM wave, when designing PWM generator in FPGA, we can also extract the following two main circuits: 1. Timer/counter circuit 2. Output comparison circuit Timer/counter circuit designThe timer circuit design is relatively simple. In "Xiao Meige FPGA Design Idea and Verification Method Video Tutorial", Lesson 04 "Counter Design and Verification" introduces the simplest counter design. Referring to the typical configuration of various MCU counters when outputting PWM wave, it can be seen that the timer/counter adopts a cyclic decreasing counting method. The counter cyclically decreases from the set initial count value to 0, and then returns to the initial count value and decreases again. In this way, you only need to set an initial count value and determine the frequency of the count clock source to determine the time for a complete count cycle, that is, the frequency of the PWM signal. In this section, we design the count clock source frequency of the timer/counter to be the output frequency of the crystal oscillator on the mainboard of the Core Route FPGA Learning Kit, which is 50MHz. The timer/counter bit width is 32 bits, and the counter code is as follows: Output comparison circuit The output comparison circuit determines the level state of the final PWM output signal by comparing the real-time count value of the counter with the set value in the comparison register. Here, we can define that when the counter count value is greater than or equal to the comparison value, the PWM output terminal outputs a low level, and when the count value is less than the comparison value, the PWM output terminal outputs a high level. Therefore, the output comparison circuit design code is as follows: Complete PWM generation circuit designThrough the above design, the main circuit of the simplest PWM generation circuit has been designed. The following is the complete code of the PWM generation circuit: PWM generation circuit simulation verificationThe verification idea of this PWM generation circuit is relatively simple. It only needs to generate a 50MHz reference counting clock source (other frequencies can also be used, just need to correct the relevant parameters in the frequency and duty cycle calculation formula), and then give the pre-reload value and output comparison value, and then enable counting to start the PWM output. During operation, modifying the pre-reload value can set the frequency of the output PWM signal and will also affect the output duty cycle. When the pre-reload value is determined, modifying the output comparison value can set the output duty cycle. The final output PWM wave frequency calculation formula is: 279221 Therefore, when the output frequency is determined, the pre-reload value can be calculated, and the calculation formula is: 279222 For example, when you want to set the output signal frequency to 5KHz, 279223 Therefore, we only need to set the counter_arr value to 9999 to make the final output signal frequency 5KHz. When the output PWM frequency is determined, its output duty cycle calculation is the quotient of the output comparison value and the pre-reload value. The calculation formula is: 279224Therefore, when the output duty cycle is determined, the output comparison value can be calculated, and the calculation formula is:
For example, when the output frequency is 5KHz and the output duty cycle is 70% PWM generation circuit testbench designAccording to the above calculation formula, the simulation file of the pwm_generator module can be designed as follows: Simulation Result AnalysisThe following figure shows the simulation waveform when the output PWM wave frequency is set to 50KHz (counter_arr is 999) and the duty cycle is 40% (counter_ccr is 400). It can be seen from the figure that the low level period is 12us, the high level period is 8us, and the entire signal period is 20us, that is, the frequency is 50KHz. The duty cycle is 8/20= 0.4. The following figure shows the simulation waveform when the output PWM wave frequency is set to 50KHz (counter_arr is 999) and the duty cycle is 70% (counter_ccr is 700). It can be seen from the figure that the low level period is 6us, the high level period is 14us, and the entire signal period is 20us, that is, the frequency is 50KHz. The duty cycle is 14/20= 0.7. The following figure shows the simulation waveform when the output PWM wave frequency is set to 100KHz (counter_arr is 499) and the duty cycle is 50% (counter_ccr is 250). It can be seen from the figure that the low level period is 5us, the high level period is 5us, and the entire signal period is 10us, that is, the frequency is 100KHz. The duty cycle is 5/10= 0.5. The following figure shows the simulation waveform when the output PWM wave frequency is set to 100KHz (counter_arr is 499) and the duty cycle is 20% (counter_ccr is 100). It can be seen from the figure that the low level period is 8us, the high level period is 2us, and the entire signal period is 10us, that is, the frequency is 100KHz. The duty cycle is 2/10 = 0.2.
It can be seen from this that the PWM generation circuit can correctly generate PWM output signals. PWM driven buzzer board-level verification Through simulation verification, we confirmed that the theoretical design of the PWM generating circuit is correct. Next, we will use the PWM generating module to drive the passive buzzer on the Core Route FPGA development board, so that the passive buzzer can emit the "Do Re Mi Fa So La Xi" tone in a cycle. (I wanted to make the buzzer play a song, but I have a negative musical talent and can't learn to compose music, so I can only play the most basic "Do Re Mi Fa So La Si". I hope friends with musical talent can compose and play beautiful music based on this.) The following are the frequencies corresponding to each tune learned from the information.
According to the frequency value of each tone, the pre-reload value of the PWM sending module can be calculated. The following is the calculated tone frequency and the pre-reload value of the corresponding frequency output by the corresponding PWM sending module. In this example, the duty cycle of the PWM wave is always kept at 50%. From the previous simulation verification, it can be seen that when the duty cycle is 50%, the output comparison value is exactly half of the pre-reload value. Therefore, we only need to divide the pre-reload value by 2 (shift right one bit) and directly assign the result to the output comparison value, so as to avoid repeated calculation of the output comparison value. In addition, in order to ensure that the switching of the tone can be easily distinguished by us, a 500ms timer is designed to switch the tone every 500ms. This part of the circuit is very simple, so the detailed design ideas of the code will not be explained in this board-level verification section, only the specific code will be given. The code of the tone playing circuit is as follows: The pin assignment of the buzzer tone playing circuit is shown in the following table: After the pin assignment is completed, compile the project and then download it to the Core Route FPGA development board. After the download is completed, the buzzer starts to play from bass 1 to treble 7 in a loop. Xiao Mei Ge Xinhangxian Electronic Studio 4.
The following figure shows the simulation waveform when the output PWM wave frequency is set to 50KHz (counter_arr is 999) and the duty cycle is 70% (counter_ccr is 700). It can be seen from the figure that the low level period is 6us, the high level period is 14us, and the entire signal period is 20us, that is, the frequency is 50KHz. The duty cycle is 14/20= 0.7. The following figure shows the simulation waveform when the output PWM wave frequency is set to 100KHz (counter_arr is 499) and the duty cycle is 50% (counter_ccr is 250). It can be seen from the figure that the low level period is 5us, the high level period is 5us, and the entire signal period is 10us, that is, the frequency is 100KHz. The duty cycle is 5/10= 0.5. The figure below shows the simulation waveform when the output PWM wave frequency is set to 100KHz (counter_arr is 499) and the duty cycle is 20% (counter_ccr is 100). It can be seen from the figure that the low-level period is 8us, the high-level period is 2us, and the entire signal period is 10us, that is, the frequency is 100KHz. The duty cycle is 2/10= 0.2.
It can be seen that the PWM generation circuit can correctly generate PWM output signals. PWM driven buzzer board-level verification Through simulation verification, we confirmed that the theoretical design of the PWM generating circuit is correct. Next, we will use the PWM generating module to drive the passive buzzer on the Core Route FPGA development board, so that the passive buzzer can emit the "Do Re Mi Fa So La Xi" tone in a cycle. (I wanted to make the buzzer play a song, but I have a negative musical talent and can't learn to compose music, so I can only play the most basic "Do Re Mi Fa So La Si". I hope friends with musical talent can compose and play beautiful music based on this.) The following are the frequencies corresponding to each tune learned from the information.
According to the frequency value of each tone, the pre-reload value of the PWM sending module can be calculated. The following is the calculated tone frequency and the pre-reload value of the corresponding frequency output by the corresponding PWM sending module. In this example, the duty cycle of the PWM wave is always kept at 50%. From the previous simulation verification, it can be seen that when the duty cycle is 50%, the output comparison value is exactly half of the pre-reload value. Therefore, we only need to divide the pre-reload value by 2 (shift right one bit) and directly assign the result to the output comparison value, so as to avoid repeated calculation of the output comparison value. In addition, in order to ensure that the switching of the tone can be easily distinguished by us, a 500ms timer is designed to switch the tone every 500ms. This part of the circuit is very simple, so the detailed design ideas of the code will not be explained in this board-level verification section, only the specific code will be given. The code of the tone playing circuit is as follows: The pin assignment of the buzzer tone playing circuit is shown in the following table: After the pin assignment is completed, compile the project and then download it to the Core Route FPGA development board. After the download is completed, the buzzer starts to play from bass 1 to treble 7 in a loop. Xiao Mei Ge Xinhangxian Electronic Studio 4.
The following figure shows the simulation waveform when the output PWM wave frequency is set to 50KHz (counter_arr is 999) and the duty cycle is 70% (counter_ccr is 700). It can be seen from the figure that the low level period is 6us, the high level period is 14us, and the entire signal period is 20us, that is, the frequency is 50KHz. The duty cycle is 14/20= 0.7. The following figure shows the simulation waveform when the output PWM wave frequency is set to 100KHz (counter_arr is 499) and the duty cycle is 50% (counter_ccr is 250). It can be seen from the figure that the low level period is 5us, the high level period is 5us, and the entire signal period is 10us, that is, the frequency is 100KHz. The duty cycle is 5/10= 0.5. The figure below shows the simulation waveform when the output PWM wave frequency is set to 100KHz (counter_arr is 499) and the duty cycle is 20% (counter_ccr is 100). It can be seen from the figure that the low-level period is 8us, the high-level period is 2us, and the entire signal period is 10us, that is, the frequency is 100KHz. The duty cycle is 2/10= 0.2.
It can be seen that the PWM generation circuit can correctly generate PWM output signals. PWM driven buzzer board-level verification Through simulation verification, we confirmed that the theoretical design of the PWM generating circuit is correct. Next, we will use the PWM generating module to drive the passive buzzer on the Core Route FPGA development board, so that the passive buzzer can emit the "Do Re Mi Fa So La Xi" tone in a cycle. (I wanted to make the buzzer play a song, but I have a negative musical talent and can't learn to compose music, so I can only play the most basic "Do Re Mi Fa So La Si". I hope friends with musical talent can compose and play beautiful music based on this.) The following are the frequencies corresponding to each tune learned from the information.
According to the frequency value of each tone, the pre-reload value of the PWM sending module can be calculated. The following is the calculated tone frequency and the pre-reload value of the corresponding frequency output by the corresponding PWM sending module. In this example, the duty cycle of the PWM wave is always kept at 50%. From the previous simulation verification, it can be seen that when the duty cycle is 50%, the output comparison value is exactly half of the pre-reload value. Therefore, we only need to divide the pre-reload value by 2 (shift right one bit) and directly assign the result to the output comparison value, so as to avoid repeated calculation of the output comparison value. In addition, in order to ensure that the switching of the tone can be easily distinguished by us, a 500ms timer is designed to switch the tone every 500ms. This part of the circuit is very simple, so the detailed design ideas of the code will not be explained in this board-level verification section, only the specific code will be given. The code of the tone playing circuit is as follows: The pin assignment of the buzzer tone playing circuit is shown in the following table: After the pin assignment is completed, compile the project and then download it to the Core Route FPGA development board. After the download is completed, the buzzer starts to play from bass 1 to treble 7 in a loop. Xiao Mei Ge Xinhangxian Electronic Studio 2. It can be seen that the PWM generation circuit can correctly generate PWM output signals. PWM drive buzzer board-level verification Through simulation verification, we confirmed that the theoretical design of the PWM generation circuit is correct. Next, we will use the PWM generation module to drive the passive buzzer on the core route FPGA development board, so that the passive buzzer can cyclically emit the tone of " 多來咪发索拉西". (I wanted to make the buzzer play a song, but I have a negative musical talent and can't learn to compose music, so I can only play the most basic "Do Re Mi Fa So La Si". I hope friends with musical talent can compose and play beautiful music based on this.) The following are the frequencies corresponding to each tune learned from the information. According to the frequency value of each tone, the pre-reload value of the PWM sending module can be calculated. The following is the calculated tone frequency and the pre-reload value of the corresponding frequency output by the corresponding PWM sending module. In this example, the duty cycle of the PWM wave is always kept at 50%. From the previous simulation verification, it can be seen that when the duty cycle is 50%, the output comparison value is exactly half of the pre-reload value. Therefore, we only need to divide the pre-reload value by 2 (shift right one bit) and directly assign the result to the output comparison value, so as to avoid repeated calculation of the output comparison value. In addition, in order to ensure that the switching of the tone can be easily distinguished by us, a 500ms timer is designed to switch the tone every 500ms. This part of the circuit is very simple, so the detailed design ideas of the code will not be explained in this board-level verification section, only the specific code will be given. The code of the tone playing circuit is as follows: The pin assignment of the buzzer tone playing circuit is shown in the following table: After the pin assignment is completed, compile the project and then download it to the Core Route FPGA development board. After the download is completed, the buzzer starts to play from bass 1 to treble 7 in a loop. Xiao Mei Ge Xinhangxian Electronic Studio 2. It can be seen that the PWM generation circuit can correctly generate PWM output signals. PWM drive buzzer board-level verification Through simulation verification, we confirmed that the theoretical design of the PWM generation circuit is correct. Next, we will use the PWM generation module to drive the passive buzzer on the core route FPGA development board, so that the passive buzzer can cyclically emit the tone of " 多來咪发索拉西". (I wanted to make the buzzer play a song, but I have a negative musical talent and can't learn to compose music, so I can only play the most basic "Do Re Mi Fa So La Si". I hope friends with musical talent can compose and play beautiful music based on this.) The following are the frequencies corresponding to each tune learned from the information. According to the frequency value of each tone, the pre-reload value of the PWM sending module can be calculated. The following is the calculated tone frequency and the pre-reload value of the corresponding frequency output by the corresponding PWM sending module. In this example, the duty cycle of the PWM wave is always kept at 50%. From the previous simulation verification, it can be seen that when the duty cycle is 50%, the output comparison value is exactly half of the pre-reload value. Therefore, we only need to divide the pre-reload value by 2 (shift right one bit) and directly assign the result to the output comparison value, so as to avoid repeated calculation of the output comparison value. In addition, in order to ensure that the switching of the tone can be easily distinguished by us, a 500ms timer is designed to switch the tone every 500ms. This part of the circuit is very simple, so the detailed design ideas of the code will not be explained in this board-level verification section, only the specific code will be given. The code of the tone playing circuit is as follows: The pin assignment of the buzzer tone playing circuit is shown in the following table: After the pin assignment is completed, compile the project and then download it to the Core Route FPGA development board. After the download is completed, the buzzer starts to play from bass 1 to treble 7 in a loop. Xiao Mei Ge Xinhangxian Electronic Studio com/link?url=fOSB7dY1oNvepIoDkSy7jK6oBaTNg3WGHKMTtqbQT2ATrLzFCcsagyLNGWo6RsaSM43UvzxjaIjcDcepI-sqFK]Do Re Mi Fa So La Xi[/url]” has been released. I hope that friends with musical talent can compose and play beautiful music based on this. The following is the frequency corresponding to each tune learned from the data. According to the frequency value of each tone, the pre-reload value of the PWM sending module can be calculated. The following is the calculated tone frequency and the pre-reload value of the corresponding frequency output by the corresponding PWM sending module. In this example, we only need to keep the duty cycle of the PWM wave at 50%. From the previous simulation verification, we know that when the duty cycle is 50%, the output comparison value is exactly half of the pre-reload value. Therefore, we only need to divide the pre-reload value by 2 (shift right one bit) and directly assign the result to the output comparison value, so as to avoid repeated calculation of the output comparison value. In addition, in order to ensure that the switching of tones can be easily distinguished, a 500ms timer is designed to switch the tone every 500ms. This part of the circuit is very simple, so the detailed design ideas of the code will not be explained in this board-level verification part, only the specific code will be given. The code of the tone playback circuit is as follows: The pin assignment of the buzzer tone playback circuit is shown in the following table: After the pin assignment is completed, compile the project and then download it to the Core Route FPGA development board. After the download is complete, the buzzer will start to play from bass 1 to treble 7 in a loop. Xiao Meige Xinhangxian Electronics Studio com/link?url=fOSB7dY1oNvepIoDkSy7jK6oBaTNg3WGHKMTtqbQT2ATrLzFCcsagyLNGWo6RsaSM43UvzxjaIjcDcepI-sqFK]Do Re Mi Fa So La Xi[/url]” has been released. I hope that friends with musical talent can compose and play beautiful music based on this. The following is the frequency corresponding to each tune learned from the data. According to the frequency value of each tone, the pre-reload value of the PWM sending module can be calculated. The following is the calculated tone frequency and the pre-reload value of the corresponding frequency output by the corresponding PWM sending module. In this example, we only need to keep the duty cycle of the PWM wave at 50%. From the previous simulation verification, we know that when the duty cycle is 50%, the output comparison value is exactly half of the pre-reload value. Therefore, we only need to divide the pre-reload value by 2 (shift right one bit) and directly assign the result to the output comparison value, so as to avoid repeated calculation of the output comparison value. In addition, in order to ensure that the switching of tones can be easily distinguished, a 500ms timer is designed to switch the tone every 500ms. This part of the circuit is very simple, so the detailed design ideas of the code will not be explained in this board-level verification part, only the specific code will be given. The code of the tone playback circuit is as follows: The pin assignment of the buzzer tone playback circuit is shown in the following table: After the pin assignment is completed, compile the project and then download it to the Core Route FPGA development board. After the download is complete, the buzzer will start to play from bass 1 to treble 7 in a loop. Xiao Meige Xinhangxian Electronics Studio
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