Current status and development of DSP chips (embedded processor comparison)

Jacktang

Current status and development of DSP chips (embedded processor comparison) [Copy link]

The first DSP chip was born in the late 1970s. The first generation of DSP chips, represented by AMI's S2811 and Intel's 2920, did not have single-cycle hardware multipliers on the chip. Characteristics of DSP chips (1) Manufacturing process Early DSPs used 4UM N-channel MOS (NMOS) process. Today's DSPs generally use submicron CMOS process, reaching 0.25um or 0.18um. The number of pins on DSP chips has increased from about 40 to more than 200. The number of peripheral circuits that need to be designed has become less and less, and the cost, size and power consumption per MIPS have all dropped significantly. (2) Memory capacity In the early 1980s, the DSPs had only a few hundred units of on-chip program memory and data memory. Some chips even had no ROM. At present, the data and program memory in the DSP chip can reach tens of K words. In addition, the addressing capability of the off-chip program memory and data memory has also been greatly enhanced, reaching 16 M&[url=http://bbs.elecfans.com/zhuti_715_1.html]TI46 bits and 4G&[url=http://bbs.elecfans.com/zhuti_715_1.html]TI40 bits or more respectively. (3) Internal structure At present, multi-bus, multi-processing unit and multi-stage pipeline structure are widely used in DSP chips. With perfect interface function, the system function, data processing ability and communication function with external devices of DSP are greatly enhanced. The CPU contains 8 parallel processing units. One clock cycle can execute 8 instructions and perform up to 1.6 billion fixed-point operations per second. (3) Running speed After nearly 20 years of development, the instruction cycle of DSP has been shortened from 400ns to less than 10ns, and the corresponding operating speed has been increased from 2.5MIPS to more than 2000MIPS. Representatively, TI's TMS320C6201 DSP takes only 66us to execute a 1024-point complex FFT operation. (4) Calculation accuracy and dynamic range 0)] Due to the dynamic range of the input signal and the problem of error accumulation that may occur in iterative algorithms, higher requirements are placed on the accuracy of single-chip DSPs.

The word length of DSPs has increased from 8 bits to 16 bits, 24 bits, and 32 bits, and the length of the accumulator has also increased to 40 bits.

The emergence of very long instruction word (VLIW) structure and high-performance floating-point DSPs has expanded the dynamic range of data processing.

（5） Development Tools

The DSPs introduced in the 1990s all had relatively complete software and hardware development tools

Simulator software emulator Emulator online emulator

C compiler

The development of high-speed, high-performance DSP devices

[color=rgb(0, 0,（6）Highly integrated

Analog-digital hybrid DSP chips that integrate filtering, A/D, D/A, ROM, RAM and DSP core will have great development and application

Low power consumption and low voltage Further reduce power consumption and develop low-voltage DSP cores (currently some DSP core voltages have dropped to 3.3V and 2.5V), making them more suitable for personal communication devices, portable computers and portable instruments.

Develop dedicated DSP chips

In order to meet the design of system-level chips, the development of ASIC based on DSP core will have great development

Provide a more complete development environment, especially a more efficient and optimized C compiler and algebraic instruction system, to overcome the shortcomings of assembly language programs with poor readability and portability, and shorten the development cycle

Expanding the application field DSP chips will penetrate into many fields such as aviation, aerospace, radar, sonar, imaging, film and television, medical equipment, and household appliances, further expanding the scope of application

Characteristics of DSP chips

(1) Harvard structure

Early microprocessors mostly used the Von-Neumann structure. The program space and data space on the chip are combined, and instruction fetching and operand fetching are both performed in time-sharing through a bus. When high-speed computing is performed, not only can instructions and operands not be fetched at the same time, but it will also cause a bottleneck in the transmission channel.

DSP uses a Harvard structure that separates program space and data space, allowing instructions (from program memory) and operands (from data memory) to be fetched at the same time. In addition, data can be transferred between program space and data space, which is an improved Harvard structure.

（2）Multi-bus structure

Many DSP chips use a multi-bus structure, which can ensure that the program space and data space can be accessed multiple times in one machine cycle.

TMS320C54x has four buses, P, C, D, and E (each bus includes an address bus and a data bus). It can fetch one instruction from the program memory, read two operands from the data memory, and write one operand to the data memory in one machine cycle, greatly improving the running speed of the DSP.

For DSP, the internal bus is a very important resource. The more buses there are, the more complex the functions that can be performed. （3） Pipeline structure DSP needs to go through several stages such as instruction fetch, decoding, operation fetch and execution to execute an instruction. In DSP, a pipeline structure is adopted. These stages are overlapped during the program running. In this way, while executing the current instruction, the operand fetch, decoding and instruction fetch of the next three instructions are also completed in sequence, reducing the instruction cycle to the minimum.

By using this pipeline structure and executing repeated operations, we can ensure that the multiplication and accumulation operations, which are most commonly used in digital signal processing, can be completed within a single instruction cycle.

(4) Multiple processing units

DSP generally includes multiple processing units, such as the arithmetic logic unit (ALU), auxiliary register operation unit (ARAU), accumulator (ACC) and hardware multiplier (MUL). They can perform operations simultaneously in one instruction cycle. For example, when executing a multiplication and accumulation, the auxiliary register unit has completed the addressing of the next address and is fully prepared for the next multiplication and accumulation operation. Therefore, when the DSP performs continuous multiplication and addition operations, each multiplication and addition operation is a single cycle. This multi-processing unit structure of DSP is particularly suitable for FIR and IIR filters. The multi-processing unit structure of many DSPs can also implement some special algorithms. For example, the bit code inversion addressing and modulus operation of FFT are implemented in hardware inside the chip to improve the running speed.arial] (5) Special DSP instructions

In order to better meet the needs of digital signal processing applications, some special DSP instructions are designed in the DSP instruction system.

The MAD (multiplication, accumulation and data movement) instruction in

has the function of executing four instructions, namely LT, DMOV, MPY and APAC.

The FIRS and LM5 instructions in TMS320C54x are specifically used for the coefficient-symmetrical F1R filter and LMS algorithm. (6) Short instruction cycle The instruction cycle of early DSPs was about 400ns, and they were manufactured using 4us NMOs. Its computing speed is 5MIPS (5 million instructions per second)

With the development of integrated circuit technology, DSP widely adopts submicron CMOS manufacturing technology, and its operating speed is getting faster and faster

The operating speed of TMS320C54x can reach 100MIPS

The clock of TMS320C6203 is 300MHZ, and the operating speed reaches 2400MIPS

(7) High calculation precision The word length of early DSP was 8 bits, which was gradually increased to 16 bits, 24 bits, and 32 bits. In order to prevent overflow during calculation, some accumulators reached 40 bits. A number of floating-point DSPs, such as TMS320C3x, TMS320C4x, ADSP21020, etc., provide a larger dynamic range. (8) Strong hardware configuration The interface functions of the new generation of DSPs are becoming stronger and stronger. The chip has serial port, host interface (HPI), DMA controller, software-controlled wait state generator, and phase-locked loop clock generator. The on-chip simulation of the test access port that complies with the IEEE 1149.1 standard makes it easier to complete system design. Many DSP chips can work in power saving mode to reduce system power consumption. Conclusion DSP chips are widely used in signal processing, image processing, instruments, voice and language, control, military, communication, medical treatment, household appliances and other fields. This article introduces the current status and development of DSP chips in detail from the aspects of manufacturing process, memory capacity, running speed, calculation accuracy and dynamic range, development tools, etc., and also briefly introduces the characteristics of DSP chips.arial] The clock of TMS320C6203 is 300MHZ, and the running speed reaches 2400MIPS

(7) High calculation accuracy

The word length of early DSP was 8 bits, which was gradually increased to 16 bits, 24 bits, and 32 bits

In order to prevent overflow during calculation, some accumulators reach 40 bits

A number of floating-point DSPs, such as TMS320C3x, TMS320C4x, ADSP21020, etc., provide a larger dynamic range. (8) Strong hardware configuration The interface functions of the new generation of DSPs are becoming stronger and stronger. The chip has a serial port, a host interface (HPI), a DMA controller, a software-controlled wait state generator, and a phase-locked loop clock generator. Implementing on-chip simulation of test access ports that comply with the IEEE 1149.1 standard makes it easier to complete system design. Many DSP chips can work in power-saving mode to reduce system power consumption. Summary DSP chips are widely used in signal processing, image processing, instruments, voice and language, control, military, communications, medical treatment, household appliances and other fields. This article introduces the current status and development of DSP chips in detail from the aspects of manufacturing process, memory capacity, operating speed, calculation accuracy and dynamic range, development tools, etc., and also briefly introduces the characteristics of DSP chips.arial] The clock of TMS320C6203 is 300MHZ, and the running speed reaches 2400MIPS

(7) High calculation accuracy

The word length of early DSP was 8 bits, which was gradually increased to 16 bits, 24 bits, and 32 bits

In order to prevent overflow during calculation, some accumulators reach 40 bits

A number of floating-point DSPs, such as TMS320C3x, TMS320C4x, ADSP21020, etc., provide a larger dynamic range. (8) Strong hardware configuration The interface functions of the new generation of DSPs are becoming stronger and stronger. The chip has a serial port, a host interface (HPI), a DMA controller, a software-controlled wait state generator, and a phase-locked loop clock generator. Implementing on-chip simulation of test access ports that comply with the IEEE 1149.1 standard makes it easier to complete system design. Many DSP chips can work in power-saving mode to reduce system power consumption. Summary DSP chips are widely used in signal processing, image processing, instruments, voice and language, control, military, communications, medical treatment, household appliances and other fields. This article introduces the current status and development of DSP chips in detail from the aspects of manufacturing process, memory capacity, operating speed, calculation accuracy and dynamic range, development tools, etc., and also briefly introduces the characteristics of DSP chips.