Design of keyboard controller based on FPGA

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Design of keyboard controller based on FPGA [Copy link]

Introduction Due to the reprogrammable nature of CPLD, the same device can be used for different keyboards and products, achieving high production and low cost, while also saving the resources of the microcontroller for other uses. The reprogrammable feature, coupled with easy-to-use design tools, allows late-stage design changes, improves product design flexibility, and reduces risk. In microcontroller application systems, using the keyboard interface to input data is the most common method for on-site real-time debugging, data adjustment, and various parameter settings. There are many ways to implement the peripheral keyboard expansion circuit of the microcontroller, such as directly using the I/O interface of the microcontroller or using the 8255A interface chip to achieve the expansion function of the peripheral keyboard. However, in these methods, the keyboard expansion circuit needs to occupy the resources of the microcontroller to monitor and process the keys, which is not easy to implement for microcontroller systems that require high real-time processing. In order to solve this problem, a dedicated keyboard interface chip can be used to expand the keyboard subsystem. However, this type of dedicated keyboard interface chip is still lacking in flexibility in use, especially when the user needs to implement certain specific functions, its shortcomings are more obvious. In view of the above problems, a 4×4 keyboard interface chip design based on Lattice's LC4128V is proposed. The software development environment used is IspLEVER. l Development environment introduction IspLEVER is the latest EDA software launched by Lattice. Design input can be done in three ways: schematic, hardware description language, and mixed input. It can perform functional simulation and timing simulation on the designed digital electronic system. The compiler is the core of this software, which can perform logic optimization, map logic to devices, automatically complete layout and routing, and generate fuse map files required for programming. The Constraints Editor tool in the software allows the selection of I/O settings and pin assignments through a graphical user interface. The lspLEVER software provides developers with a simple and powerful tool for designing all Lattice programmable logic products. 2 Keyboard controller design 2.1 Design of 4×4 keyboard controller based on LC4128V Figure 1 shows the design of 4×4 keyboard controller (KEYPADCTL) based on Lattice's programmable logic device LC4128V.

According to the scanning principle of the keyboard, the output pins R1~R4 (row scan lines) of the keyboard controller output low level in turn and set the corresponding keyboard row low. When a key is pressed, the corresponding input c1~c4 (column reply line) is also set low. Then, according to the corresponding relationship between the low level of the row and column, the key value pressed can be determined by encoding. Output K0~K3 is the key value waiting to be read by the microcontroller. INT outputs the interrupt signal of the microcontroller, notifying the microcontroller to read the key value. CLK is the clock signal of the controller, and cLR is the reset signal of the controller. 2.2 Internal schematic diagram and working principle of its main parts The keyboard controller is composed of keyboard scanning circuit, encoder circuit, keyboard debounce circuit, divider circuit, counter circuit and key value latch, as shown in Figure 2. (1) The keyboard scanning circuit is a state machine that can self-start to the required state. When the system is powered on and a valid reset signal CLR is input at the same time, the output terminals R1~R4 (L1~L4) of the scanning circuit will output the following scanning levels 1110, 1101, 1011, 0111 in turn according to the design requirements. L1~L4, as the input of the encoder, participate in the encoding through the corresponding relationship with the column reply line (C1~C4). However, R1~R4 is the keyboard row scanning line that adds the high level to L1~L4 to enable the three-state gate output. The row scan line is added with a three-state gate output to prevent the high and low levels of the LC4128V pins from being shorted when two or more keys on a column are pressed at the same time. If this happens, it will not only affect the accuracy of the keyboard controller, but more seriously, it will burn out the programmable logic device LC4128V. Therefore, the controller outputs the row scan line through a three-state gate. The enable signal of the three-state gate is the inversion of the signal it passes, so that the high level of the output will be in a high-impedance state. By connecting a pull-up resistor to each row line of the keyboard, the same output signal as L1~L4 can be obtained. This processing not only meets the design needs, but also plays a role in protecting the device. EN is the enable input terminal of the scan circuit, and the high level is valid. It is obtained by ANDing the column reply line after de-jittering. When a key is pressed, the corresponding column line will be set low. The result of the ANDing is low, which stops the scan circuit from scanning and waits for the controller to process the scan result, obtain the corresponding key value and send it to the key value latch, waiting for the microcontroller to read it. The advantage of this is that it can prevent the controller from missing the reading of the key. According to debugging, the keyboard scan clock signal is better to be more than four times the de-jitter circuit clock. Therefore, CLK is obtained by dividing the de-jitter circuit clock. Figure 3 shows the specific schematic diagram of the scanning circuit. (2) The design uses a 4×4 keyboard with 16 key states, plus a state where no key is pressed, for a total of 17 states, while a 4-bit binary number can only represent 16 states. To solve this problem, R4 and L4 are ORed and then ORed with the interrupt signal generated by the counter to generate a single-chip microcomputer interrupt. When the last key is pressed, the keyboard controller generates an interrupt, allowing the single-chip microcomputer to read the key value 0000 (this state is also when no key is pressed), thereby distinguishing the no-key state from the last key pressed state. In this way, only the status information of the first 15 keys need to be considered during encoding. Finally, a 4-bit binary number can be used to represent the status of all keys. Figure 4 shows the specific schematic diagram of the encoder. (3) The keyboard de-bounce circuit is mainly composed of two DQ flip-flops and one basic RS flip-flop. When a key is pressed, the corresponding column line should ideally remain at a low level. However, jitter is inevitable in practical applications, and the column reply line will have high-level jumps of varying lengths. The keyboard de-bounce circuit is to remove the interference of such jittering high levels on key value detection. In order to eliminate such interference, the de-bounce circuit adopts a two-stage delay strategy. As long as the duration of the jittering high level is within two clock cycles of the de-bounce circuit, this jitter will not be introduced into the encoding circuit. The specific schematic diagram of the keyboard debounce circuit is shown in Figure 5.

3 Simulation experiment and analysis 3.1 Output simulation waveform of the scanning circuit The output simulation waveform of the keyboard controller scanning circuit is shown in Figure 6. In Figure 6, the output end of the scanning circuit outputs a low level in turn to scan each row of the keyboard. In the figure, L1~L4 is the output of the scanner without a three-state gate, which serves as the input of the encoding circuit. R1~R4 is the output waveform of the three-state gate. It can be seen from Figure 3 that when the output of L1~L4 is a high level, the output state of R1~R4 is high impedance.

[img=499,330]http://editerupload.eaw.com.When two keys on the same column are pressed at the same time, the illegal situation of high and low level short circuit on the two pins of the programmable logic device LC4128V can be avoided. 3.2 Encoder simulation waveform The encoder simulation waveform is shown in Figure 7.

In Figure 7, when the first row of the keyboard scan level is low, according to the scanning principle of the 4×4 keyboard, C1 can only be low when the first key of the first column is pressed. The corresponding encoding circuit output K3K2K1KO value is 0001. Only when the first key in the second column is pressed, C2 can be low, and the value of K3K2K1K0 is 0010. Similarly, when C3 and C4 are low, the values of K3K2K1K0 are 0011 and 0100 respectively. The key values of the first 15 keys can be obtained by encoding in this way, and the key value of the 16th key will generate a microcontroller interrupt signal after the phase-OR of R4 and L4 is not performed, notifying the microcontroller to read its key value 0000. 3.3 Simulation waveform of de-jitter circuit The simulation waveform of the de-jitter circuit is shown in Figure 8.

In Figure 8, when jitter occurs during keystroke, DELYOUT1 remains at a low level after being processed by the de-jitter circuit. It can be seen that jitter has no effect on the reading of key values. 3.4 Overall simulation waveform of keyboard controller The overall simulation waveform of keyboard controller is shown in Figure 9. Figure 9 shows the input/output waveform of the keyboard controller when the keyboard row scan signal sets the second row of the keyboard low and the second key in the first column is pressed. As can be seen from Figure 9, the key value detected by the controller is 0101 (the encoding value of this key). This value is not immediately latched into the key value latch when a key is detected to be pressed. Instead, after a period of delay, the keyboard controller sends an interrupt signal (INT) to the microcontroller to read the key value, and at the same time gives the latch a latch signal to latch this value. This can not only prevent key misoperation, but also handle the situation where the key is pressed for a long time. 4 Conclusion The powerful in-system programming capability of LC4128V of IspMACH 4000 series, with the strong support of IspLEVER series tool software, can realize the interface design of embedded system in a very short time, and can make embedded products more flexible. Reality shows that the development and wide application of programmable logic devices are bringing revolutionary changes to the design of computers and their application systems. The keyboard controller designed in this paper has been applied to a real embedded product, which greatly increases the upgrade space of the product and saves the resources of the single-chip computer, and has achieved very good results.