Analyze the working principle, advantages and disadvantages of the SPI interface

1. Interface

The SPI interface is often called a 4-wire serial bus and works in a master/slave manner, with the data transfer process initiated by the host. As shown in Figure 1, the four signal lines used are:

1) SCLK: Serial clock, used to synchronize data transmission, output by the host;

2) MOSI: host output slave input data line;

3) MISO: Host input and slave output data lines;

4) SS: Chip select line, active low level, output by the host.

On the SPI bus, multiple slaves can appear at a certain time, but only one master can exist. The master determines the slave to communicate through the chip select line. This requires the MISO port of the slave to have three-state characteristics, so that the port line behaves as high impedance when the device is not gated.

2. Data transmission

Within one SPI clock cycle, the following operations will be completed:

1) The host sends 1 bit of data through the MOSI line, and the slave reads the 1 bit of data through the line;

2) The slave sends 1-bit data through the MISO line, and the host reads the 1-bit data through this line.

This is accomplished using a shift register. As shown in Figure 2, the master and the slave each have a shift register, and the two are connected in a ring. With the clock pulse, data is moved out of the master register and slave register in sequence from high bit to low bit, and moved into slave register and master register in sequence. When all the contents in the register are moved out, it is equivalent to completing the exchange of the contents of the two registers.

3. Clock polarity and clock phase

In SPI operation, the two most important settings are clock polarity (CPOL or UCCKPL) and clock phase (CPHA or UCCKPH). The clock polarity sets the level of the clock when it is idle, and the clock phase sets the clock edges on which data is read and data is sent.

The sending data of the master and the slave is completed at the same time, and the receiving data of both is also completed at the same time. Therefore, in order to ensure correct communication between master and slave, their SPI should have the same clock polarity and clock phase.

For example, select MSP430 controller and OLED driver SH1101A as master and slave respectively. Figure 3 and Figure 4 show their SPI timing. As can be seen from Figure 4, the SPI clock of SH1101A is high level when idle and receives data on the back clock edge. The setting of the MSP430 controller SPI should be consistent with this. As can be seen from Figure 3, to make the clock high level when idle, UCCKPL should be set to 1; to receive data on the back clock edge, UCCKPH should be cleared.

4. Advantages and Disadvantages

The SPI interface has the following advantages:

1) Support full-duplex operation;

2) Easy to operate;

3) The data transfer rate is high.