Sample/hold (S/H) circuit diagram

The sample/hold (S/H) circuit is shown in the figure. CP is the sampling/holding pulse. When CP is "0", the analog switch SE1 is open, SE2 and SE3 are closed, and the operational amplifiers A1 and A2 are connected in series to form a large loop feedback circuit. At this time, Uout=Uin, the charging voltage on the capacitor C For Uin, the sampling phase is completed. When CP is "1", SE1 is closed, SE2 and SE3 are disconnected, the operational amplifier A1 forms a voltage follower, and the output terminal is disconnected from A2, so that the capacitor C has no discharge circuit, and the LJN voltage is maintained at C, so Uout= Uin, until the second sampling.