Peak voltage sample and hold circuit

The peak voltage sample and hold circuit is shown in the figure. The peak voltage sampling and holding circuit consists of a sampling and holding chip LF398 and a voltage
comparator LM311 . The output voltage and input voltage of LF398 are compared through LM311. When V. > , LM311 outputs
high level and sends it to the logic control terminal ⑧ pin of LF398, making LF398 in the sampling state; when V. When it reaches its peak and then decreases. V,<V, the voltage
comparator LM311 outputs low level, and the logic control terminal of LF398 is set to low level, so that LF398 is in a holding state. Since LM311 uses
an open-collector output, a pull-up resistor is required. The pulse sent from the output end of the overvoltage detection circuit controls the conduction of the circuit switch.
When there is no overvoltage, the sampling capacitor is discharged. Otherwise, the sampling circuit keeps tracking the changes in the peak value.