Odd-frequency counter with symmetrical output waveform (μL9020)

As shown in the figure, the frequency divider circuit can be triggered for sine waves, square waves or positive pulses as long as the peak value reaches between 0.5 and 5V. The operating frequency of the circuit can reach 40MHz. The input signal of the frequency divider drives the J-K trigger through the limiting amplifier Q1 and finally outputs through the buffer Q2. The transistor Q1 is to provide an appropriate trigger level for the first stage of frequency division. When driven at a high level, the capacitor C1 can play a current limiting role. If the driving level is low, the capacity of C1 can be increased to increase the triggering ability. The output stage Q2 can prevent the frequency divider from being affected by the capacitive load.