| Part Number | Manufacturer | Description | Datasheet |
|---|---|---|---|
| HC89S105S8T6 | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit microcontroller designed and developed with high-speed and low-power CMOS technology. It has 64KBytes FLASH program memory, 256 Bytes IRAM and 2K Bytes XRAM, 41 bidirectional I/O ports, and 1 peripheral function pin fully mapped module PTM. 2 16-bit timers/counters, 2 PCA modules, 3 sets of 12-bit complementary PWM with dead zone control, 2 UART communication ports, 1 IIC communication port, 1 SPI communication port, 1 RTC circuit, 15 External interrupt, 23+2 channels 12-bit ADC, four system operating modes (normal, low frequency, power down and idle) and 16 interrupt sources | download |
| HC89S105C8T6 | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit microcontroller designed and developed with high-speed and low-power CMOS technology. It has 64KBytes FLASH program memory, 256 Bytes IRAM and 2K Bytes XRAM, 41 bidirectional I/O ports, and 1 peripheral function pin fully mapped module PTM. 2 16-bit timers/counters, 2 PCA modules, 3 sets of 12-bit complementary PWM with dead zone control, 2 UART communication ports, 1 IIC communication port, 1 SPI communication port, 1 RTC circuit, 15 External interrupt, 23+2 channels 12-bit ADC, four system operating modes (normal, low frequency, power down and idle) and 16 interrupt sources | download |
| HC89F302B | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit touch microcontroller designed and developed with high-speed and low-power CMOS technology. It has 16K Bytes FLASH program memory, 256 Bytes IRAM and 512 Bytes XRAM. It has up to 22 bidirectional I/O ports and 1 peripheral function pin is fully mapped. Module PTM, 4 16-bit timers/counters, 1 set of 12-bit complementary PWM with dead zone control, 1 8-bit PWM, 1 UART, 1 SPI, 1 IIC, up to 4 external interrupts, up to 12 channels Capacitive touch button detection, 13+2 channels 12-bit ADC, four system operating modes (normal, low speed, power down and idle) and 14 interrupt sources | download |
| HC89F303B | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit touch microcontroller designed and developed with high-speed and low-power CMOS technology. It has 16K Bytes FLASH program memory, 256 Bytes IRAM and 512 Bytes XRAM, 26 bidirectional I/O ports, and 1 peripheral function pin fully mapped module. PTM, 4 16-bit timers/counters, 1 set of 12-bit complementary PWM with dead zone control, 1 8-bit PWM, 1 UART, 1 SPI, 1 IIC, 4 external interrupts, 16-channel capacitive touch buttons Detection, 16+2 channels 12-bit ADC, four system operating modes (normal, low speed, power down and idle) and 14 interrupt sources | download |
| HC89F3421 | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit touch microcontroller designed and developed with high-speed and low-power CMOS technology. It has 16K Bytes FLASH program memory, 256 Bytes IRAM and 1K Bytes XRAM, 14 bidirectional I/O ports, and 1 peripheral function pin fully mapped module. PTM, 5 16-bit timers/counters, 3 groups of 12-bit complementary PWM with dead zone control, 1 8-bit PWM, 2 UARTs, 1 SPI, 1 IIC, 14 external interrupts, 7-channel capacitive touch buttons Detection, up to 7+2 channels of 12-bit ADC, four system operating modes (normal, low speed, power down and idle) and 19 interrupt sources | download |
| HC89F3531 | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit touch microcontroller designed and developed with high-speed and low-power CMOS technology. It has 32K Bytes FLASH program memory, 256 Bytes IRAM and 1K Bytes XRAM. It has up to 22 bidirectional I/O ports and 1 peripheral function pin is fully mapped. Module PTM, 5 16-bit timers/counters, 3 groups of 12-bit complementary PWM with dead zone control, 1 8-bit PWM, 2 UARTs, 1 SPI, 1 IIC, up to 22 external interrupts, up to 12 channels Capacitive touch button detection, up to 13+2 channels of 12-bit ADC, four system operating modes (normal, low speed, power down and idle) and 19 interrupt sources | download |
| HC89F3541 | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit touch microcontroller designed and developed with high-speed and low-power CMOS technology. It has 32K Bytes FLASH program memory, 256 Bytes IRAM and 1K Bytes XRAM. It has up to 30 bidirectional I/O ports and 1 peripheral function pin is fully mapped. Module PTM, 5 16-bit timers/counters, 3 groups of 12-bit complementary PWM with dead zone control, 1 8-bit PWM, 2 UARTs, 1 SPI, 1 IIC, 26 external interrupts, 16-channel capacitive touch | download |
| HC89F3650 | Shanghai Holychip Electronic Co., Ltd. | Enhanced 8-bit microcontroller designed and developed with high-speed and low-power CMOS technology, internal 64KBytes FLASH program memory, 256 Bytes IRAM and 2K Bytes XRAM, 46/42 bidirectional I/O ports, 1 peripheral function pin fully mapped module PTM , 2 16-bit timers/counters, 2 PCA modules, 3 sets of 12-bit complementary PWM with dead zone control, 2 UARTs, 1 IIC, 1 SPI, 1 RTC, 16 external interrupts, 24 capacitors Touch button detection, 24+2 channels 12-bit ADC, four system working modes (normal, low speed, power down and idle) and 17 interrupt sources | download |
| HC89S905 | Shanghai Holychip Electronic Co., Ltd. | An enhanced 8-bit microcontroller designed and developed with high-speed and low-power CMOS technology. It has 16K Bytes FLASH program memory, 256 Bytes IRAM and 256 Bytes XRAM, up to 18 bidirectional I/O ports, and 1 peripheral function pin fully mapped module. PTM, 5 16-bit timers/counters, 3 sets of 12-bit complementary PWM with dead zone control, 1 8-bit PWM, 2 UARTs, 1 SPI, 16 external interrupts, 11+2 channels of 12-bit ADC, four three system operating modes (normal, low frequency, power down and idle) and 16 interrupt sources | download |
| KF8F4230SD | ChipON | KF8F4230 is a reduced instruction CPU with Harvard architecture. The chip integrates a variety of peripherals, including: 1 8-bit timer/counter T0 1 16-bit timer/counter T1 2 16-bit timers T2/T3 1 12-bit 10/12/14 channel ADC module 1 5-bit 2 output channel DAC module 2 8-bit PWM modules 1 CCP (capture/compare/PWM5) module 2 analog comparator modules 1 operational amplifier module (KF8F4230 does not have operational amplifier module) 1 USART module 1 SSCI (I2C/SPI) module, a 2V/3V/4V optional reference voltage hardware watchdog (with software enablement), low voltage detection and low voltage reset module integrated into the chip (1024+16) × 8 bits User data memory RAM, 16K bytes of program memory and 128×8-bit DATA EEPROM. | download |
| KF8F2320SD | ChipON | KF8F2320 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, an 8-bit timer T2, two 8-bit PWM modules, a 12-bit 8 Channel AD module, 2 analog comparator modules, hardware watchdog and low voltage detection and low voltage reset modules, etc. The chip integrates 272×8-bit data memory RAM, 2K×16-bit program memory and 256x8 DATA EEPROM. | download |
| KF8F2320SB | ChipON | KF8F2320 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, an 8-bit timer T2, two 8-bit PWM modules, a 12-bit 8 Channel AD module, 2 analog comparator modules, hardware watchdog and low voltage detection and low voltage reset modules, etc. The chip integrates 272×8-bit data memory RAM, 2K×16-bit program memory and 256x8 DATA EEPROM. | download |
| KF8F1000SD | ChipON | KF8F1000 is a Harvard structured reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed in one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, an 8-bit timer T2, 2-channel 8-bit PWM modules, hardware watchdog, low voltage detection and low voltage reset modules, etc. The chip integrates 272×8-bit data memory RAM, 1K×16-bit program memory and 256x8 DATA EEPROM. | download |
| KF8F1000SB | ChipON | KF8F1000 is a Harvard structured reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed in one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, an 8-bit timer T2, 2-channel 8-bit PWM modules, hardware watchdog, low voltage detection and low voltage reset modules, etc. The chip integrates 272×8-bit data memory RAM, 1K×16-bit program memory and 256x8 DATA EEPROM. | download |
| KF8F1020SAR | ChipON | KF8F1020 is a general control MCU. The program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer T0, a 16-bit timer T1, a 16-bit timer T2, a 12-bit 3-channel AD module, hardware watchdog and low voltage Detection and low voltage reset module, etc. The chip integrates 144×8-bit data memory RAM, 1K×16-bit program memory and 64×16-bit BEE | download |
| KF8F333-TS28 | ChipON | KF8F333 is a Harvard architecture reduced instruction CPU. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, an 8-bit timer and a 16-bit timer/counter T1, two 8-bit PWM modules, and one 10-bit enhanced PWM module, 1 full-duplex asynchronous communication module, 2 analog comparator modules, 1 8-way capacitive touch module, 1 10-bit 12-channel AD module, 1 operational amplifier module, hardware watchdog and low voltage detection and Low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM | download |
| KF8F333-SS28 | ChipON | KF8F333 is a Harvard architecture reduced instruction CPU. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, an 8-bit timer and a 16-bit timer/counter T1, two 8-bit PWM modules, and one 10-bit enhanced PWM module, 1 full-duplex asynchronous communication module, 2 analog comparator modules, 1 8-way capacitive touch module, 1 10-bit 12-channel AD module, 1 operational amplifier module, hardware watchdog and low voltage detection and Low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM | download |
| KF8F333-S28 | ChipON | KF8F333 is a Harvard architecture reduced instruction CPU. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, an 8-bit timer and a 16-bit timer/counter T1, two 8-bit PWM modules, and one 10-bit enhanced PWM module, 1 full-duplex asynchronous communication module, 2 analog comparator modules, 1 8-way capacitive touch module, 1 10-bit 12-channel AD module, 1 operational amplifier module, hardware watchdog and low voltage detection and Low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM | download |
| KF8F312M4-SS20 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312M4-S20 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312M4-S14 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312M4-S8 | ChipON | KF8F312M4 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-TS20 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-SS20 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-S8 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-S20 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F312-S14 | ChipON | KF8F312 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 4K×16-bit program memory | download |
| KF8F310-S20 | ChipON | KF8F310 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed in one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, 2-channel 8-bit PWM modules, 2 operational amplifiers, a 10-bit 8-channel AD module, and a hardware monitor. Watchdog and low voltage detection and low voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F310-S16 | ChipON | KF8F310 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed in one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, 2-channel 8-bit PWM modules, 2 operational amplifiers, a 10-bit 8-channel AD module, and a hardware monitor. Watchdog and low voltage detection and low voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 4K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F213-TS20 | ChipON | KF8F213 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Operational amplifier, an analog comparator module, a 10-bit 8-channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 2K×16-bit program memory. | download |
EEWorld
subscription
account
EEWorld
service
account
Automotive
development
circle
Robot
development
community
京公网安备 11010802033920号
EEWORLD
