| Part Number | Manufacturer | Description | Datasheet |
|---|---|---|---|
| KF8F213-SS20 | ChipON | KF8F213 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Operational amplifier, an analog comparator module, a 10-bit 8-channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 2K×16-bit program memory. | download |
| KF8F213-S20 | ChipON | KF8F213 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Operational amplifier, an analog comparator module, a 10-bit 8-channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 2K×16-bit program memory. | download |
| KF8F213-S16 | ChipON | KF8F213 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Operational amplifier, an analog comparator module, a 10-bit 8-channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM and 2K×16-bit program memory. | download |
| KF8F212-S8-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S8 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-SS20-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-SS20 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S20-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S20 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F212-S14-5 | ChipON | KF8F212 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including 2 8-bit timers/counters T0 and T2, 1 16-bit timer/counter T1, 2 8-bit PWM modules, 1 10-bit enhanced PWM module, 1 Universal full-duplex asynchronous communication module, 2 analog comparator modules, 2 operational amplifier modules, 1 10-bit 12/8/4 channel AD module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F211-S8 | ChipON | KF8F211 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including two 8-bit timers/counters T0 and T2, a 16-bit timer/counter T1, a 10-bit enhanced PWM module, an analog comparator module, a 10-bit 8-channel AD module, hardware watchdog, low-voltage detection and low-voltage reset module, etc. The chip integrates 256×8-bit data memory RAM and 2K×16-bit program memory. | download |
| KF8F210-S8 | ChipON | KF8F210 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte KF8F210 is a Harvard structure reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, 2 8-bit PWM modules, 2 operational amplifiers, a 10-bit 8/7/8/4 Channel AD module, hardware watchdog, low voltage detection and low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F210-S16 | ChipON | KF8F210 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte KF8F210 is a Harvard structure reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, 2 8-bit PWM modules, 2 operational amplifiers, a 10-bit 8/7/8/4 Channel AD module, hardware watchdog, low voltage detection and low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F210-S14 | ChipON | KF8F210 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte KF8F210 is a Harvard structure reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, 2 8-bit PWM modules, 2 operational amplifiers, a 10-bit 8/7/8/4 Channel AD module, hardware watchdog, low voltage detection and low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F210-S20 | ChipON | KF8F210 is a reduced instruction CPU with Harvard architecture. In this structure, the program and data buses are independent of each other. The instruction byte KF8F210 is a Harvard structure reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, 2 8-bit PWM modules, 2 operational amplifiers, a 10-bit 8/7/8/4 Channel AD module, hardware watchdog, low voltage detection and low voltage reset module, etc. The chip integrates 256×8-bit data memory RAM, 2K×16-bit program memory and 128×16-bit BLOCK EEPROM. | download |
| KF8F207SB | ChipON | KF8F207 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, an 8-bit timer T2, 2 8-bit PWM modules, and 2 analog comparators Modules, hardware watchdogs, low-voltage detection and low-voltage reset modules, etc. The chip integrates 272×8-bit data memory RAM, 2K×16-bit program memory and 256x8 DATA EEPROM. | download |
| KF8L20Z08TN | ChipON | KF8L20 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed in one machine cycle. There are 73 instructions in total, which is highly efficient and easy to expand. The KF8L20 chip integrates a variety of peripherals, including: 1 8-bit timer/counter T0 1 16-bit timer T1 1 16-bit timer T2 1 16-bit timer/counter T3 1 16-bit timer Counter/Counter T4 1 12-bit 6-channel external (+2 internal) channel ADC module 1 8×19 dot matrix LCD driver module temperature sensor hardware watchdog (with software enable) low voltage detection low voltage reset in the chip Integrating (256+16)×8-bit data memory RAM and 256×8-bit DATA EEPROM, KF8L20Z04TN integrates 6KB program memory | download |
| KF8L12Z08SE01 | ChipON | KF8L12Z08 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including: 1 8-bit timer T0; 1 16-bit timer/counter T1; 1 16-bit timer/counter T2; 1 16-bit timer T3; 4 channels of 8 Bit PWM module (KF8L12Z08SE01 provides 2 channels); 1 5-channel 12-bit ADC module; 1 SSCI (SPI/I2C) module; 1 photoelectric detector (PCD) module; hardware watchdog and low voltage detection and low voltage Reset module, etc.; The chip integrates 400(384+16)×8-bit data memory RAM and 8K byte program memory | download |
| KF8L12Z08SE | ChipON | KF8L12Z08 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed within one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including: 1 8-bit timer T0; 1 16-bit timer/counter T1; 1 16-bit timer/counter T2; 1 16-bit timer T3; 4 channels of 8 Bit PWM module (KF8L12Z08SE01 provides 2 channels); 1 5-channel 12-bit ADC module; 1 SSCI (SPI/I2C) module; 1 photoelectric detector (PCD) module; hardware watchdog and low voltage detection and low voltage Reset module, etc.; The chip integrates 400(384+16)×8-bit data memory RAM and 8K byte program memory | download |
| KF8L10Z08OG | ChipON | KF8L10Z08 is a Harvard architecture reduced instruction CPU. In this structure, the program and data buses are independent of each other. The instruction byte length is 16 bits, and most instructions can be executed in one machine cycle. There are 68 instructions in total, which is highly efficient and easy to expand. The chip integrates a variety of peripherals, including: 1 8-bit timer T0; 1 16-bit timer/counter T1; 1 16-bit timer/counter T2; 1 16-bit timer T3; 4 channels of 8 1-bit PWM module; 1 12-bit ADC module; 2 comparator modules; 1 SSCI (SPI/I2C) module; hardware watchdog and low-voltage detection and low-voltage reset modules, etc.; 400 (384+) are integrated into the chip 16)×8-bit data memory RAM, 8K byte program memory | download |
| KF8TS2716QP | ChipON | KF8TS2716 is a Harvard architecture reduced instruction CPU. The KF8TS2716 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, a 12-bit 10/14/14-channel AD module, 2 8-bit PWM modules, a 14/18/22-channel capacitive touch module, 1 SSCI (I2C/SPI) module, 1 universal full-duplex serial port (USART ) module, an 8×8 LED driver module, a 16-channel Vbias bias output module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 1040(1024+16)×8-bit user data memory and 8K×16-bit program memory. | download |
| KF8TS2716UN | ChipON | KF8TS2716 is a Harvard architecture reduced instruction CPU. The KF8TS2716 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, a 12-bit 10/14/14-channel AD module, 2 8-bit PWM modules, a 14/18/22-channel capacitive touch module, 1 SSCI (I2C/SPI) module, 1 universal full-duplex serial port (USART ) module, an 8×8 LED driver module, a 16-channel Vbias bias output module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 1040(1024+16)×8-bit user data memory and 8K×16-bit program memory. | download |
| KF8TS2716TN | ChipON | KF8TS2716 is a Harvard architecture reduced instruction CPU. The KF8TS2716 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, a 12-bit 10/14/14-channel AD module, 2 8-bit PWM modules, a 14/18/22-channel capacitive touch module, 1 SSCI (I2C/SPI) module, 1 universal full-duplex serial port (USART ) module, an 8×8 LED driver module, a 16-channel Vbias bias output module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 1040(1024+16)×8-bit user data memory and 8K×16-bit program memory. | download |
| KF8TS2716SN | ChipON | KF8TS2716 is a Harvard architecture reduced instruction CPU. The KF8TS2716 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, a 12-bit 10/14/14-channel AD module, 2 8-bit PWM modules, a 14/18/22-channel capacitive touch module, 1 SSCI (I2C/SPI) module, 1 universal full-duplex serial port (USART ) module, an 8×8 LED driver module, a 16-channel Vbias bias output module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 1040(1024+16)×8-bit user data memory and 8K×16-bit program memory. | download |
| KF8TS2714SG | ChipON | KF8TS2716 is a Harvard architecture reduced instruction CPU. The KF8TS2716 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, a 12-bit 10/14/14-channel AD module, 2 8-bit PWM modules, a 14/18/22-channel capacitive touch module, 1 SSCI (I2C/SPI) module, 1 universal full-duplex serial port (USART ) module, an 8×8 LED driver module, a 16-channel Vbias bias output module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 1040(1024+16)×8-bit user data memory and 8K×16-bit program memory. | download |
| KF8TS2710SE | ChipON | KF8TS2716 is a Harvard architecture reduced instruction CPU. The KF8TS2716 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, a 12-bit 10/14/14-channel AD module, 2 8-bit PWM modules, a 14/18/22-channel capacitive touch module, 1 SSCI (I2C/SPI) module, 1 universal full-duplex serial port (USART ) module, an 8×8 LED driver module, a 16-channel Vbias bias output module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 1040(1024+16)×8-bit user data memory and 8K×16-bit program memory. | download |
| KF8TS2708SD | ChipON | KF8TS2716 is a Harvard architecture reduced instruction CPU. The KF8TS2716 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, a 12-bit 10/14/14-channel AD module, 2 8-bit PWM modules, a 14/18/22-channel capacitive touch module, 1 SSCI (I2C/SPI) module, 1 universal full-duplex serial port (USART ) module, an 8×8 LED driver module, a 16-channel Vbias bias output module, hardware watchdog and low-voltage detection and low-voltage reset modules, etc. The chip integrates 1040(1024+16)×8-bit user data memory and 8K×16-bit program memory. | download |
| KF8TS2516TN | ChipON | KF8TS2508/2510/2514 is a reduced instruction CPU with Harvard architecture. The KF8TS2508/2510/2514 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, and a 16-bit timer/counter. T4, a 12-bit 8/10/14-channel AD module, two 8-bit PWM modules, an 8/10/14-channel capacitive touch module, an I2C module, internal reference voltage module, hardware watchdog and low Voltage detection and low voltage reset module, etc. The chip integrates 400×8-bit user data memory and 4K×16-bit program memory. Note: KF8TS2508 has 8 AD channels and 8 capacitive touch channels; KF8TS2510 has 10 AD channels and 10 capacitive touch channels; KF8TS2514 has 14 AD channels and 14 capacitive touch channels; | download |
| KF8TS2516SN | ChipON | KF8TS2508/2510/2514 is a reduced instruction CPU with Harvard architecture. The KF8TS2508/2510/2514 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, and a 16-bit timer/counter. T4, a 12-bit 8/10/14-channel AD module, two 8-bit PWM modules, an 8/10/14-channel capacitive touch module, an I2C module, internal reference voltage module, hardware watchdog and low Voltage detection and low voltage reset module, etc. The chip integrates 400×8-bit user data memory and 4K×16-bit program memory. Note: KF8TS2508 has 8 AD channels and 8 capacitive touch channels; KF8TS2510 has 10 AD channels and 10 capacitive touch channels; KF8TS2514 has 14 AD channels and 14 capacitive touch channels; | download |
| KF8TS3514NG | ChipON | KF8TS3510/3514 is a Harvard architecture reduced instruction CPU. The KF8TS3510/3514 chip integrates a variety of peripherals, including an 8-bit timer/counter T0, a 16-bit timer/counter T1, a 16-bit timer T3, a 16-bit timer/counter T4, 1 12-bit 8/10/14-channel AD module, 1 comparator module, 1 operational amplifier module, 2 8-bit PWM modules, an 8/10/14-channel capacitive touch module, 1 I2C module, internal Reference voltage module, hardware watchdog, low voltage detection and low voltage reset module, etc. The chip integrates 400×8-bit user data memory and 4K×16-bit program memory. Note: KF8TS3510 has 10 AD channels and 10 capacitive touch channels; KF8TS3514 has 14 AD channels and 14 capacitive touch channels; | download |
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