2.5 MSPS, 20-Bit
Σ∆
ADC
Preliminary Technical Data
FEATURES
High performance 20-bit Sigma-Delta ADC
118dB SNR at 78kHz output data rate
100dB SNR at 2.5MHz output data rate
2.5 MHz maximum fully filtered output word rate
Programmable over-sampling rate (8x to 256x)
Flexible parallel interface
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low pass FIR filter with default or user programmable
coefficients
Over-range alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power down modes
Synchronization of multiple devices via SYNC pin
VIN- VIN+
AD7760
FUNCTIONAL BLOCK DIAGRAM
AVDD1
AVDD2
AVDD3
AVDD4
DECAP
RBIAS
AGND
Programmable
Decimation
Control Logic,
I/O and
Registers
FIR Filter
Engine
VDRIVE
DVDD
DGND
DIFF
VREF+
+
BUF
-
Multi-Bit
Sigma-Delta
Modulator
Reconstruction
AD7760
MCLK
MCLK
SYNC
RESET
RD/WR
DRD
Y
CS
DB0 - DB15
Figure 1.
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
PRODUCT OVERVIEW
The AD7760 high performance 20-bit sigma delta analog to
digital converter combines wide input bandwidth and high
speed with the benefits of sigma delta conversion with
performance of 100dB SNR at 2.5MSPS making it ideal for high
speed data acquisition. Wide dynamic range combined with
significantly reduced anti-aliasing requirements simplify the
design process. An integrated buffer to drive the reference, a
differential amplifier for signal buffering and level shifting, an
over-range flag, internal gain & offset registers and a low-pass
digital FIR filter make the AD7760 a compact highly integrated
data acquisition device requiring minimal peripheral
component selection. In addition the device offers
programmable decimation rates and the digital FIR filter can be
adjusted if the default characteristics are not appropriate to the
application. The AD7760 is ideal for applications demanding
high SNR without necessitating design of complex front end
signal processing.
The differential input is sampled at up to 40MS/s by an analog
modulator. The modulator output is processed by a series of
low-pass filters, the final one having default or user
programmable coefficients. The sample rate, filter corner
frequencies and output word rate are set by a combination of
the external clock frequency and the configuration registers of
the AD7760.
The reference voltage supplied to the AD7760 determines the
analog input range. With a 4V reference, the analog input range
is ±3.2V differential biased around a common mode of 2V. This
common mode biasing can be achieved using the on-chip
differential amplifiers, further reducing the external signal
conditioning requirements.
The AD7760 is available in an exposed paddle 64-lead TQFP
and 48-lead CSP packages and is specified over the industrial
temperature range from -40°C to +85°C.
Rev. PrN
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7760
TABLE OF CONTENTS
TABLE OF CONTENTS.................................................................. 2
AD7760—Specifications.................................................................. 3
Timing Specifications....................................................................... 5
Timing Diagrams.............................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Functional Descriptions.......................... 8
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 12
AD7760 Interface............................................................................ 13
Preliminary Technical Data
Clocking the AD7760..................................................................... 14
Driving The AD7760...................................................................... 15
Using The AD7760..................................................................... 16
Bias Resistor Selection ............................................................... 16
Programmable FIR Filter............................................................... 17
Downloading a User-Defined Filter ............................................ 18
Example Filter Download ......................................................... 18
AD7760 Registers ........................................................................... 20
Non Bit-Mapped Registers........................................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
Rev. PrN | Page 2 of 22
Preliminary Technical Data
AD7760—SPECIFICATIONS
Table 1. V
DD1
= 2.5 V, V
DD2
= 5 V, V
REF
= 4.096 V, T
A
= +25°C, Full Power Mode, unless otherwise noted
Parameter
DYNAMIC PERFORMANCE
Decimate by 256
Signal to Noise Ratio (SNR)
1
Spurious Free Dynamic Range (SFDR)
1
Total Harmonic Distortion (THD)
1
Intermodulation Distortion (IMD)
1
Decimate by 16
Signal to Noise Ratio (SNR)
1
Spurious Free Dynamic Range (SFDR)
1
Total Harmonic Distortion (THD)
1
Intermodulation Distortion (IMD)
1
Decimate by 8
Signal to Noise Ratio (SNR)
1
Spurious Free Dynamic Range (SFDR)
1
Total Harmonic Distortion (THD)
1
Intermodulation Distortion (IMD)
1
Intermodulation Distortion (IMD)
1
DC ACCURACY
Resolution
Integral Nonlinearity
1
Differential Nonlinearity
1
Offset Error
1
Gain Error
1
Offset Error Drift
Gain Error Drift
DIGITAL FILTER RESPONSE
Decimate by 8
Group Delay
Decimate by 16
Group Delay
Decimate by 128
Group Delay
ANALOG INPUT
Differential Input Voltage
DC Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
V
REF
Input Voltage
V
REF
Input DC Leakage Current
V
REF
Input Capacitance
POWER REQUIREMENTS
AV
DD1
(Modulator Supply)
AV
DD2
(General Supply)
AV
DD3
(Diff-Amp Supply)
AV
DD4
(Ref Buffer Supply)
DV
DD
V
DRIVE
Test Conditions/Comments
MCLK = 24.576MHz, ODR = 48kHz, FIN = 1kHz Sine Wave
Non-harmonic
Input Amplitude = -6dB
MCLK = 40MHz, ODR = 1.25MHz, FIN =100kHz Sine Wave
Non-harmonic
Input Amplitude = -6dB
MCLK = 40MHz, ODR = 2.5MHz, FIN = 100kHz Sine Wave
Non-harmonic
Input Amplitude = -6dB
FIN = 100kHz Sine Wave
FIN = 1MHz Sine Wave
100
100
-100
-100
-100
20
1
1
0.03
5
0.0006
0.1
103
103
-100
-100
118
118
-100
-100
Specifcation
Unit
AD7760
dB typ
dBFS typ
dB typ
dB typ
dB typ
dBFS typ
dB typ
dB typ
dB typ
dBFS typ
dB typ
dB typ
dB typ
Bits
LSB typ
LSB typ
% typ
LSB typ
% /°C
LSB /°C
At 18 bits
Guaranteed monotonic to 20 bits
MCLK = 40MHz
MCLK = 40MHz
MCLK = 24.576MHz
Vin(+) – Vin(-), V
REF
= 2.5V
Vin(+) – Vin(-), V
REF
= 4.096V
With internal buffer
With external buffer
V
DD3
= 3.3V
V
DD3
= 5V
12
24
480
±2
±3.25
±2
5
55
+2.5
+4.096
±1
5
+2.5
+5
+3.0/+5.5
+3.15/+5.25
+2.5
+1.65/+2.7
Rev. PrN | Page 3 of 22
µS typ
µS typ
µS typ
V pk-pk
V pk-pk
µA max
pF typ
pF typ
Volts
Volts
µA max
pF max
Volts
Volts
V min/max
V min/max
Volts
V min/max
±5%
±5%
±5%
AD7760
Parameter
Full Power Mode
AI
DD1
(Modulator)
AI
DD2
(General)
AI
DD4
(Reference Buffer)
Low Power Mode
AI
DD1
(Modulator)
AI
DD2
(General)
AI
DD4
(Reference Buffer)
AI
DD3
(Diff Amp)
D
IDD
Standby Mode
AI
DD1
(Modulator)
AI
DD2
(General)
AI
DD3
(Diff Amp)
AI
DD4
(Reference Buffer)
D
IDD
POWER DISSIPATION
Full Power Mode
Modulator (P
1
)
General (P
2
)
Reference Buffer (P
4
)
Test Conditions/Comments
Preliminary Technical Data
Specifcation
Unit
AV
DD4
= +5V
50
35
35
mA typ
mA typ
mA typ
AV
DD4
= +5V
AV
DD3
= +5V, Both Modes
Both Modes
26
20
10
42
45
210
30
30
30
250
690
mA typ
mA typ
mA typ
mA typ
mA typ
µA typ
nA typ
nA typ
nA typ
µA typ
µA typ
AV
DD3
= +5V
AV
DD4
= +5V
Clock Stopped
Clock Running
AV
DD4
= +3.3V
AV
DD4
= +5V
125
175
101
175
mW typ
mW typ
mW typ
mW typ
Low Power Mode
Modulator (P
1
)
General (P
2
)
Reference Buffer (P
4
)
Differential Amplifier (P
3
)
Digital Power
Standby Mode
AV
DD4
= +3.3V
AV
DD4
= +5V
AV
DD3
= +3.3V
AV
DD3
= +5V
Clock Stopped
Clock Running
65
100
27
50
116
210
112.5
1.2
2.3
mW typ
mW typ
mW typ
mW typ
mW typ
mW typ
mW typ
mW typ
mW typ
1
See Terminology
Rev. PrN | Page 4 of 22
Preliminary Technical Data
TIMING SPECIFICATIONS
AD7760
Table 2.
V
DD1
= 2.5 V, V
DD2
= 5 V, V
REF
= 4.096 V, V
DRIVE
= TBD V, T
A
= +25°C, C
LOAD
= 25pF, Full Power Mode, unless otherwise noted
Parameter
f
MCLK
f
ICLK
t
11
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
Limit at T
MIN
, T
MAX
12.288
80
12.288
20
0.5 × t
ICLK
10
2
10
t
ICLK
t
ICLK
2
10
0.5 × t
ICLK
0.5 × t
ICLK
15
TBD
TBD
10
t
ICLK
t
ICLK
10
10
Unit
MHz min
MHz max
MHz min
MHz max
typ
nS min
nS min
nS typ
min
min
nS min
nS max
typ
typ
nS typ
xS min
xS min
nS max
xS min
xS min
nS min
nS min
Description
Applied Master Clock Frequency
Internal Modulator Clock Derived from MCLK.
DRDY Pulse Width
DRDY Falling Edge to CS falling Edge
RD/WR Setup Time to CS Falling Edge
Data Access Time
CS Low Pulse Width
CS High Pulse Width Between Reads
RD/WR Hold Time to CS Rising Edge
Bus Relinquish Time
DRDY High Period
DRDY Low Period
Data Access Time
Data Valid Prior to DRDY Rising Edge
Data Valid After DRDY Rising Edge
Bus Relinquish Time
CS Low Pulse Width
CS High Period Between Address and Data
Data Setup Time
Data Hold Time
1
t
ICLK
= 1/f
ICLK
Rev. PrN | Page 5 of 22
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