AT49LH00B4-33TC datasheet, PDF

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AT49LH00B4-33TC: Description4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory; Categorystorage storage; File Size262KB，36 Pages; ManufacturerAtmel (Microchip)

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AT49LH00B4-33TC Overview

4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory

AT49LH00B4-33TC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	TSOP1
package instruction	10 X 20 MM, PLASTIC, MO-142CD, TSOP1-40
Contacts	40
Reach Compliance Code	compli
ECCN code	EAR99
Maximum access time	11 ns
Other features	TOP BOOT BLOCK
startup block	TOP
command user interface	YES
Data polling	NO
JESD-30 code	R-PDSO-G40
JESD-609 code	e0
length	18.4 mm
memory density	4194304 bi
Memory IC Type	FLASH
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of departments/size	7,1,1,2
Number of terminals	40
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP40,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Department size	64K,32K,16K,8K
Maximum standby current	0.000035 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	NO
type	NOR TYPE
width	10 mm

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Features

•

Complies with Intel

Low-Pin Count (LPC) Interface Specification Revision 1.1

•

– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles

Auto-detection of FWH and LPC Memory Cycles

– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets

– Can Be Used as LPC Flash for Non-Intel Chipsets

Top Boot with Bottom Partitioned Memory Array for Efficient Vital Data Storage

– 64-Kbyte Top Boot Sector, Six 64-Kbyte Sectors, One 32-Kbyte Sector, One

16-Kbyte Sector, Two 8-Kbyte Sectors

– Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing

Two Configurable Interfaces

– FWH/LPC Interface for In-System Operation

– Address/Address Multiplexed (A/A Mux) Interface for Programming during

Manufacturing

FWH/LPC Interface

– Operates with the 33 MHz PCI Bus Clock

– 5-signal Communication Interface Supporting Byte Reads and Writes

– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All

Other Sectors

– Five General-purpose Input (GPI) Pins for System Design Flexibility

– Identification (ID) Pins for Multiple Device Selection

– Sector Locking Registers for Individual Sector Read and Write Protection

A/A Mux Interface

– 11-pin Multiplexed Address and 8-pin Data Interface

– Facilitates Fast In-System or Out-of-System Programming

Single Voltage Operation

– 3.0V to 3.6V Supply Voltage for Read and Write Operations

Industry-Standard Package Options

– 32-lead PLCC

– 40-lead TSOP

•

4-megabit

Top Boot,

Bottom

Partitioned

Firmware Hub

and Low-Pin

Count Flash

Memory

AT49LH00B4

Description

The AT49LH00B4 is a Flash memory device designed for use in PC and notebook

BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec-

ification, providing support for both FWH and LPC memory read and write cycles. The

device can also automatically detect the memory cycle type to allow the AT49LH00B4

to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.

Pin Configurations

PLCC

GPI2 [A8]

GPI3 [A9]

RST [RST]

VCC

CLK [R/C]

GPI4 [A10]

[IC] IC

[A10] GPI4

[R/C] CLK

VCC

[RST] RST

[A9] GPI3

[A8] GPI2

[A7] GPI1

[A6] GPI0

[A5] WP

[A4] TBL

TSOP

GND

VCC

FWH4/LFRAME [WE]

INIT [OE]

RES [RDY/BSY]

RES [I/O7]

RES [I/O6]

RES [I/O5]

RES [I/O4]

VCC

GND

FWH3/LAD3 [I/O3]

FWH2/LAD2 [I/O2]

FWH1/LAD1 [I/O1]

FWH0/LAD0 [I/O0]

ID0 [A0]

ID1 [A1]

ID2 [A2]

ID3 [A3]

[I/O1] FWH1/LAD1

[I/O2] FWH2/LAD2

GND

[I/O3] FWH3/LAD3

[I/O4] RES

[I/O5] RES

[I/O6] RES

[A7] GPI1

[A6] GPI0

[A5] WP

[A4] TBL

[A3] ID3

[A2] ID2

[A1] ID1

[A0] ID0

[I/O0] FWH0/LAD0

IC [IC]

GND

VCC

INIT [OE]

FWH4/LFRAME [WE]

RES [RDY/BSY]

RES [I/O7]

Note:

[ ] Designates A/A Mux Interface.

3379B–FLASH–9/03

The sectoring of the AT49LH00B4’s memory array has been optimized to meet the needs of

today’s BIOS applications. By optimizing the size of the sectors, the BIOS code memory space

can be used more efficiently. Because certain BIOS code modules must reside in their own

sectors by themselves, the wasted and unused memory space that occurred with previous

generation BIOS Flash memory devices can be greatly reduced. This increased memory

space efficiency allows additional BIOS routines to be developed and added while still main-

taining the same overall device density.

The memory array of the AT49LH00B4 can be sectored in two ways simply by using two differ-

ent erase commands. Using one erase command allows the device to contain a total of eleven

sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16-

Kbyte sector, and two 8-Kbyte sectors. The 64-Kbyte boot sector is located at the top (upper-

most) of the device’s memory address space and can be hardware write protected by using

the TBL pin. Alternatively, by using a different erase command, the memory array can be

arranged into eight even erase sectors of 64-Kbyte each.

The AT49LH00B4 supports two hardware interfaces: The FWH/LPC interface for In-System

operations and the A/A Mux interface for programming during manufacturing. The Interface

Configuration (IC) pin of the device provides the control between these two interfaces. An

internal Command User Interface (CUI) serves as the control center between the device inter-

faces and the internal operation of the nonvolatile memory. A valid command sequence

written to the CUI initiates device automation.

Specifically designed for use in 3-volt systems, the AT49LH00B4 supports read, program, and

erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required

for programming and erasing.

The AT49LH00B4 utilizes fixed program and erase times, independent of the number of pro-

gram and erase cycles that have occurred. Therefore, the system does not need to be

calibrated or correlated to the cumulative number of program and erase cycles.

Block Diagram

TBL

INIT

CLK

FWH4/LFRAME

FWH/LAD[3:0]

ID[3:0]

GPI[4:0]

RST

R/C

A[10:0]

I/O[7:0]

RDY/BSY

FWH/LPC

INTERFACE

CONTROL LOGIC

I/O BUFFERS

AND LATCHES

ADDRESS LATCH

INTERFACE CONTROL

AND LOGIC

Y-DECODER

Y-GATING

A/A MUX

INTERFACE

X-DECODER

FLASH

MEMORY

ARRAY

AT49LH00B4

3379B–FLASH–9/03

AT49LH00B4-33TC Related Products

	AT49LH00B4-33TC	AT49LH00B4	AT49LH00B4-33JC
Description	4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory	4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory	4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory
Is it Rohs certified?	incompatible	-	incompatible
Maker	Atmel (Microchip)	-	Atmel (Microchip)
Parts packaging code	TSOP1	-	QFJ
package instruction	10 X 20 MM, PLASTIC, MO-142CD, TSOP1-40	-	QCCJ, LDCC32,.5X.6
Contacts	40	-	32
Reach Compliance Code	compli	-	compli
ECCN code	EAR99	-	EAR99
Maximum access time	11 ns	-	11 ns
Other features	TOP BOOT BLOCK	-	TOP BOOT BLOCK
startup block	TOP	-	TOP
command user interface	YES	-	YES
Data polling	NO	-	NO
JESD-30 code	R-PDSO-G40	-	R-PQCC-J32
JESD-609 code	e0	-	e0
length	18.4 mm	-	13.97 mm
memory density	4194304 bi	-	4194304 bi
Memory IC Type	FLASH	-	FLASH
memory width	8	-	8
Humidity sensitivity level	3	-	2
Number of functions	1	-	1
Number of departments/size	7,1,1,2	-	7,1,1,2
Number of terminals	40	-	32
word count	524288 words	-	524288 words
character code	512000	-	512000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS
Maximum operating temperature	85 °C	-	85 °C
organize	512KX8	-	512KX8
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TSOP1	-	QCCJ
Encapsulate equivalent code	TSSOP40,.8,20	-	LDCC32,.5X.6
Package shape	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	-	CHIP CARRIER
Parallel/Serial	PARALLEL	-	PARALLEL
Peak Reflow Temperature (Celsius)	240	-	225
power supply	3.3 V	-	3.3 V
Programming voltage	3 V	-	3 V
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	1.2 mm	-	3.556 mm
Department size	64K,32K,16K,8K	-	64K,32K,16K,8K
Maximum standby current	0.000035 A	-	0.000035 A
Maximum slew rate	0.06 mA	-	0.06 mA
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	3 V	-	3 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	OTHER	-	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	J BEND
Terminal pitch	0.5 mm	-	1.27 mm
Terminal location	DUAL	-	QUAD
Maximum time at peak reflow temperature	30	-	30
switch bit	NO	-	NO
type	NOR TYPE	-	NOR TYPE
width	10 mm	-	11.43 mm

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