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74AC11SCX

Description
Logic Gates Trp 3-Input AND Gate
Categorylogic    logic   
File Size290KB,9 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74AC11SCX Overview

Logic Gates Trp 3-Input AND Gate

74AC11SCX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instruction0.150 INCH, MS-012, SOIC-14
Contacts14
Reach Compliance Codeunknown
Is SamacsysN
seriesAC
JESD-30 codeR-PDSO-G14
JESD-609 codee3
length8.6235 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeAND GATE
MaximumI(ol)0.012 A
Humidity sensitivity level1
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply3.3/5 V
Prop。Delay @ Nom-Sup10 ns
propagation delay (tpd)10 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.753 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
74AC11 — Triple 3-Input AND Gate
January 2008
74AC11
Triple 3-Input AND Gate
Features
I
CC
reduced by 50%
Outputs source/sink 24mA
General Description
The AC11 contains three, 3-input AND gates.
Ordering Information
Order
Number
74AC11SC
74AC11SJ
74AC11MTC
74AC11PC
Package
Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
, C
n
O
n
Description
Inputs
Outputs
©1988 Fairchild Semiconductor Corporation
74AC11 Rev. 1.6.1
www.fairchildsemi.com

74AC11SCX Related Products

74AC11SCX 74AC11SJX 74AC11MTC
Description Logic Gates Trp 3-Input AND Gate Logic Gates Trp 3-Input AND Gate Logic Gates Trp 3-Input AND Gate
Is it Rohs certified? conform to conform to conform to
Maker Fairchild Fairchild Fairchild
Parts packaging code SOIC SOIC TSSOP
package instruction 0.150 INCH, MS-012, SOIC-14 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14 4.40 MM, MO-153AB, TSSOP-14
Contacts 14 14 14
Reach Compliance Code unknown compliant unknown
series AC AC AC
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609 code e3 e3 e3
length 8.6235 mm 10.2 mm 5 mm
Load capacitance (CL) 50 pF 50 pF 50 pF
Logic integrated circuit type AND GATE AND GATE AND GATE
MaximumI(ol) 0.012 A 0.012 A 0.012 A
Humidity sensitivity level 1 1 1
Number of functions 3 3 3
Number of entries 3 3 3
Number of terminals 14 14 14
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP TSSOP
Encapsulate equivalent code SOP14,.25 SOP14,.3 TSSOP14,.25
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TAPE AND REEL TAPE AND REEL RAIL
Peak Reflow Temperature (Celsius) 260 260 260
power supply 3.3/5 V 3.3/5 V 3.3/5 V
Prop。Delay @ Nom-Sup 10 ns 10 ns 10 ns
propagation delay (tpd) 10 ns 10 ns 10 ns
Certification status Not Qualified Not Qualified Not Qualified
Schmitt trigger NO NO NO
Maximum seat height 1.753 mm 2.1 mm 1.2 mm
Maximum supply voltage (Vsup) 6 V 6 V 6 V
Minimum supply voltage (Vsup) 2 V 2 V 2 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm 0.65 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 3.9 mm 5.3 mm 4.4 mm
Base Number Matches 1 1 1
Is Samacsys N N -
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