MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC990/991 is a 3.3V compatible, PLL based ECL/PECL clock
driver. The fully differential design ensures optimum skew and PLL jitter
performance. The performance of the MPC990/991 makes the device
ideal for Workstation, Mainframe Computer and Telecommunication
applications. The MPC990 and MPC991 devices are identical except in
the interface to the reference clock for the PLL. The MPC990 offers an
on–board crystal oscillator as the PLL reference while the MPC991 offers
a differential ECL/PECL input for applications which need to lock to an
existing clock signal. Both designs offer a secondary single–ended ECL
clock for system test capabilities.
MPC990
MPC991
LOW VOLTAGE
PLL CLOCK DRIVER
•
•
•
•
•
•
•
Fully Integrated PLL
Output Frequency Up to 400MHz
ECL/PECL Inputs and Outputs
Operates from a 3.3V Supply
Output Frequency Configurable
TQFP Packaging
±50ps
Cycle–to–Cycle Jitter
The MPC990/991 offers three banks of outputs which can each be
FA SUFFIX
programmed via the the four fsel pins of the device. There are 16 different
52–LEAD TQFP PACKAGE
output frequency configurations available in the device. The
CASE 848D–03
configurations include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and
4:3:2. The programming table in this data sheet illustrates the various
programming options. The SYNC output monitors the relationship
between the Qa and Qc output banks. The output pulses per the timing
diagrams in this data sheet signal the coincident edges of the two output
banks. This feature is useful for non binary relationships between output frequencies (i.e., 3:2 or 4:3 relationships). The Sync_Sel
input toggles the Qd outputs between sync signals and extensions to the Qc bank of outputs.
The MPC990/991 provides a separate output for the feedback to the PLL. This allows for the feedback frequency to be
programmed independently of the other outputs allowing for unique input vs output frequency relationships. The fselFB inputs
provide 6 different feedback frequencies from the QFB differential output pair.
The MPC990/991 features an external differential ECL/PECL feedback to the PLL. This external feedback feature allows for
the MPC991’s use as a “zero” delay buffer. The propagation delay between the input reference and the output is dependent on
the input reference frequency. The selection of higher reference frequencies will provide near zero delay through the device.
The PLL_En, Ref_Sel and the Test_Clk input pins provide a means of bypassing the PLL and driving the output buffers
directly. This allows the user to single step a design during system debug. Note that the Test_Clk input is routed through the
dividers so that depending on the programming several edges on the Test_Clk input will be needed to get corresponding edge
transitions on the outputs. The VCO_Sel input provides a means of recentering the VCO to provide a broader range of VCO
frequencies for stable PLL operation.
If the frequency select or the VCO_Sel pins are changed during operation, a master reset signal must be applied to ensure
output synchronization and phase–lock. If the VCO is driven beyond its maximum frequency, the VCO can outrun the internal
dividers when the VCO_Sel pin is low. This will also prevent the PLL from achieving lock. Again, a master reset signal will need to
be applied to allow for phase–lock. The device employs a power–on reset circuit which will ensure output synchronization and
PLL lock on initial power–up.
2/97
©
Motorola, Inc. 1997
1
REV 2
MPC990 MPC991
ECL DC CHARACTERISTICS
(TA = 0° to 70°C, VCCA = VCCI = VCCO = 0V, GNDI = –3.3V
±5%,
Note 1.)
0°C
Symbol
VOH
VOL
VIH
VIL
VPP
VCMR
IIH
Characteristic
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Minimum Input Swing
Common Mode Range
Input HIGH Current
Min
–1.3
–2.0
–1.1
–1.8
500
VCC
–1.3V
VCC
–0.5V
150
Typ
Max
–0.7
–1.4
–0.9
–1.5
Min
–1.3
–2.0
–1.1
–1.8
500
VCC
–1.3V
VCC
–0.5V
150
25°C
Typ
–1.0
–1.7
Max
–0.7
–1.4
–0.9
–1.5
Min
–1.3
–2.0
–1.1
–1.8
500
VCC
–1.3V
VCC
–0.5V
150
240
70°C
Typ
Max
–0.7
–1.4
–0.9
–1.5
Unit
V
V
V
V
mV
V
µA
mA
IGNDI
Power Supply Current
200
240
200
240
200
1. Refer to Motorola Application Note AN1545/D “Thermal
Data for MPC Clock Drivers”
for thermal management guidelines.
PECL DC CHARACTERISTICS
(TA = 0° to 70°C, VCCA = VCCI = VCCO = 3.3V
±5%,
GNDI = 0V, Note 2.)
0°C
Symbol
VOH
VOL
VIH
VIL
VPP
VCMR
IIH
Characteristic
Output HIGH Voltage (Note 3.)
Output LOW Voltage (Note 3.)
Input HIGH Voltage (Note 3.)
Input LOW Voltage (Note 3.)
Minimum Input Swing
Common Mode Range
Input HIGH Current
Min
2.0
1.3
2.2
1.5
500
VCC
–1.3V
VCC
–0.5V
150
Typ
Max
2.6
1.9
2.4
1.8
Min
2.0
1.3
2.2
1.5
500
VCC
–1.3V
VCC
–0.5V
150
25°C
Typ
2.3
1.6
Max
2.6
1.9
2.4
1.8
Min
2.3
1.3
2.2
1.5
500
VCC
–1.3V
VCC
–0.5V
150
240
70°C
Typ
Max
2.6
1.9
2.4
1.8
Unit
V
V
V
V
mV
V
µA
mA
IGNDI
Power Supply Current
200
240
200
240
200
2. Refer to Motorola Application Note AN1545/D “Thermal
Data for MPC Clock Drivers”
for thermal management guidelines.
3. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
AC CHARACTERISTICS
(TA = 0° to 70°C, VCCA = VCCI = VCCO = 3.3V
±5%,
Termination of 50Ω to VCC – 2.0V)
Symbol
fxtal
tr, tf
tpw
tos
fVCO
tpd
fmax
Characteristic
Crystal Oscillator Frequency
Output Rise/Fall Time
Output Duty Cycle
Output-to-Output Skew
PLL VCO Lock Range
Ref to Feedback Offset
Maximum Output Frequency Qa,Qb,Qc (÷2)
Qa,Qb,Qc (÷4)
Qa,Qb,Qc (÷6)
Qa,Qb,Qc (÷8)
Cycle–to–Cycle Jitter (Peak–to–Peak)
±50
Same Frequency
Different Frequencies
VCO_Sel = ‘0’
VCO_Sel = ‘1’
400
200
75
250
Min
10
0.2
47.5
50
150
250
Typ
Max
25
1.0
52.5
250
350
800
400
425
400
200
133
100
Unit
MHz
ns
%
ps
MHz
ps
MHz
FB
÷8
to
÷32
(Note 4.)
FB
÷4
to
÷32
fref = 50MHz (Note 5.)
20% to 80%
Condition
tjitter
ps
tlock
Maximum PLL Lock Time
10
ms
4. With VCO_Sel = ‘0’, the PLL will be unstable with a
÷2, ÷4
or
÷6
feedback ratio. With VCO_Sel = ‘1’, the PLL will be unstable with a
÷2
feedback
ratio.
5. tpd is specified for 50MHz input reference FB
÷8.
The window will shrink/grow proportionally from the minimum limit with shorter/longer input
reference periods. The tpd does not include jitter.
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
Embedded System
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