Hardware Specification
MPC860EC/D
Rev. 6.1, 11/2002
MPC860 Family
Hardware Specifications
This document contains detailed information on power consideratio
electrical characteristics, and AC timing specifications for the MPC
This document contains the following topics:
Topic
Part I, “Overview”
Part II, “Features”
Part III, “Maximum Tolerated Ratings”
Part IV, “Thermal Characteristics”
Part V, “Power Dissipation”
Part VI, “DC Characteristics”
Part VII, “Thermal Calculation and Measurement”
Part VIII, “Layout Practices”
Part IX, “Bus Signal Timing”
Part X, “IEEE 1149.1 Electrical Specifications”
Part XI, “CPM Electrical Characteristics”
Part XII, “UTOPIA AC Electrical Specifications”
Part XIII, “FEC Electrical Characteristics”
Part XIV, “Mechanical Data and Ordering Information”
Part XV, “Document Revision History”
Part I Overview
The MPC860 Quad Integrated Communications Controller (Power
is a versatile one-chip integrated microprocessor and peripheral co
designed for a variety of controller applications. It particularly exc
communications and networking systems. The PowerQUICC unit is
as the MPC860 in this manual.
The MPC860 is a derivative of Motorola’s MC68360 Quad
Communications Controller (QUICC
™
), referred to here as the Q
implements the PowerPC architecture. The CPU on the MPC860
Features
MPC8xx core that incorporates memory management units (MMUs) and instructio
data caches and that implements the PowePC instruction set. The communic
processor module (CPM) from the MC68360 QUICC has been enhanced by the addi
the inter-integrated controller (I
2
C) channel. The memory controller has been enh
enabling the MPC860 to support any type of memory, including high-perfor
memories and new types of DRAMs. A PCMCIA socket controller supports up
sockets. A real-time clock has also been integrated.
Table 1 shows the functionality supported by the members of the MPC860 family.
Table 1. MPC860 Family Functionality
Cache (Kbytes)
Part
Instruction
Cache
4
4
16
4
4
4
16
4
Data Cache
4
4
8
4
4
4
8
4
Ethernet
ATM
10T
Up to 2
Up to 2
Up to 2
Up to 4
Up to 4
Up to 4
Up to 4
1
10/100
—
1
1
—
—
1
1
1
—
yes
yes
—
yes
yes
yes
yes
2
2
2
4
4
4
4
1
1
1,2,3
1,2,3
1
1,2
1,2,3
1,2,3
4
SCC
Ref.
1
MPC860DE
MPC860DT
MPC860DP
MPC860EN
MPC860SR
MPC860T
MPC860P
MPC855T
1
Supporting documentation for these devices refers to the following:
1. MPC860 PowerQUICC User’s Manual (MPC860UM/D, Rev. 1).
2. MPC8XX ATM Supplement (MPC860SARUM/AD).
3. MPC860T (Rev. D), Fast Ethernet Controller Supplement (MPC860TREVDSUPP).
4. MPC855T User’s Manual (MPC855TUM/D, Rev. 1).
Part II Features
The following list summarizes the key MPC860 features:
•
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without
conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table
– 16-Kbyte instruction caches are four-way, set-associative with 256 sets
4-Kbyte instruction caches are two-way, set-associative with 128 sets.
– 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyt
caches are two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 1
(4-word) cache blocks.
2
MPC860 Family Hardware Specifications
MOT
Fe
•
•
•
•
•
•
– Caches are physically addressed, implement a least recently used (LRU
replacement algorithm, and are lockable on a cache block basis.
— Instruction and data caches are two-way, set-associative, physically addre
LRU replacement, and lockable on-line granularity.
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbyt
virtual address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Operates at up to 80 MHz
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 15 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM,
other memory devices.
— DRAM controller programmable to support most size and speed memory
interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte to 256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
MOTOROLA
MPC860 Family Hardware Specifications
Features
•
•
•
•
— Decrementer, time base, and real-time clock (RTC) from the PowerPC
architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standar
available when using ATM over UTOPIA interface)
ATM support compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support en
OAM and software implementation of other protocols).
— ATM pace control (APC) scheduler, providing direct support for constant b
(CBR) and unspecified bit rate (UBR) and providing control mechanisms
enabling software support of available bit rate (ABR)
— Physical interface support for UTOPIA (10/100-Mbps is not supported wi
interface) and byte-aligned serial (for example, T1/E1/ADSL)
— UTOPIA-mode ATM supports level-1 master with cell-level handshake,
multi-PHY (up to 4 physical layer devices), connection to 25-, 51-, or 155-
framers, and UTOPIA/system clock ratios of 1/2 or 1/3.
— Serial-mode ATM connection supports transmission convergence (TC) fun
for T1/E1/ADSL lines; cell delineation; cell payload scrambling/descram
automatic idle/unassigned cell insertion/stripping; header error control (H
generation, checking, and statistics.
Communications processor module (CPM)
— RISC communications processor (CP)
— Communication-specific commands (for example,
GRACEFUL STOP TRANS
ENTER HUNT MODE
, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial chann
— Up to 8Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
4
MPC860 Family Hardware Specifications
MOT
Fe
•
•
•
•
•
•
— Three parallel I/O registers with open-drain capability
Four baud-rate generators (BRGs)
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
Four serial communications controllers (SCCs)
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps opera
(available only on specially programmed devices).
— HDLC/SDLC (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (
Two SMCs (serial management channels)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
One I
2
C (inter-integrated circuit) port
— Supports master and slave modes
— Multiple-master environment support
Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed ope
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate,
defined
— 1- or 8-bit resolution
MOTOROLA
MPC860 Family Hardware Specifications
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