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9LPRS501YGLFT

Description
Microprocessor Circuit, PDSO64, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size265KB,28 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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9LPRS501YGLFT Overview

Microprocessor Circuit, PDSO64, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64

9LPRS501YGLFT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
Contacts64
Reach Compliance Codecompliant
JESD-30 codeR-PDSO-G64
JESD-609 codee3
length17 mm
Number of terminals64
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR CIRCUIT
Base Number Matches1
Datasheet
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR + INTEGRATED SERIES RESISTOR
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator and Internal series resistor on differential outputs,
PCIe Gen 1 compliant
ICS9LPRS501
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 250ps
+/- 100ppm frequency accuracy on CPU & SRC
clocks
Output Features:
2 - CPU differential low power push-pull pairs
10 - SRC differential low power push-pull pairs
1 - CPU/SRC selectable differential low power push-pull
pair
1 - SRC/DOT selectable differential low power push-pull
pair
5 - PCI, 33MHz
1 - PCI_F, 33MHz free running
1 - USB, 48MHz
1 - REF, 14.318MHz
Features/Benefits:
Does not require external pass transistor for voltage
regulator
Integrated series resistors on differential outputs,
Z
o
=50Ω
Supports spread spectrum modulation, default is 0.5%
down spread
Uses external 14.318MHz crystal, external crystal
load caps are required for frequency tuning
One differential push-pull pair selectable between
SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
0
0
0
0
1
1
1
1
2
TSSOP Pin Configuration
U
SB
MHz
DOT
MHz
FS
L
B
B0b6
0
0
1
1
0
0
1
1
1
FS
L
A
B0b5
0
1
0
1
0
1
0
1
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC
MHz
PCI
MHz
REF
MHz
100.00
33.33
14.318
48.00
96.00
Reserved
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
PCI0/CR#_A 1
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
PCI3 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96_IO 12
DOTT_96/SRCT0 13
DOTC_96/SRCC0 14
GND 15
VDD 16
SRCT1/SE1 17
SRCC1/SE2 18
GND 19
VDDPLL3_IO 20
SRCT2/SATAT 21
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
SRCC3/CR#_D 25
VDDSRC_IO 26
SRCT4 27
SRCC4 28
GNDSRC 29
SRCT9 30
SRCC9 31
SRCC11/CR#_G 32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0
CPUC0
GNDCPU
CPUT1_F
CPUC1_F
VDDCPU_IO
NC
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
VDDSRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
GNDSRC
SRCT6
SRCC6
VDDSRC
PCI_STOP#/SRCT5
CPU_STOP#/SRCC5
VDDSRC_IO
SRCC10
SRCT10
SRCT11/CR#_H
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
9LPRS501
1121F—02/23/09
1

9LPRS501YGLFT Related Products

9LPRS501YGLFT 9LPRS501YKLFT
Description Microprocessor Circuit, PDSO64, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64 Microprocessor Circuit, PQCC64, ROHS COMPLIANT, PLASTIC, MLF-64
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP DFN
package instruction 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64 ROHS COMPLIANT, PLASTIC, MLF-64
Contacts 64 64
Reach Compliance Code compliant compliant
JESD-30 code R-PDSO-G64 S-PQCC-N64
JESD-609 code e3 e3
length 17 mm 9 mm
Number of terminals 64 64
Maximum operating temperature 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP HVQCCN
Package shape RECTANGULAR SQUARE
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1 mm
Maximum supply voltage 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface MATTE TIN MATTE TIN
Terminal form GULL WING NO LEAD
Terminal pitch 0.5 mm 0.5 mm
Terminal location DUAL QUAD
Maximum time at peak reflow temperature 30 30
width 6.1 mm 9 mm
uPs/uCs/peripheral integrated circuit type MICROPROCESSOR CIRCUIT MICROPROCESSOR CIRCUIT
Base Number Matches 1 1
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