Jitter Attenuator & FemtoClock NG Multiplier
®
813N2532
Datasheet
Description
The 813N2532 device uses IDT's fourth generation FemtoClock
®
NG technology for optimal high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The 813N2532 is a PLL based
synchronous multiplier that is optimized for PDH or SONET to
Ethernet clock jitter attenuation and frequency translation.
The 813N2532 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports commercial temperature range.
Features
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Fourth generation FemtoClock
®
NG technology
Two LVPECL output pairs
Output frequencies: 19.44MHz, 25MHz, 125MHz, 155.52MHz
and 156.25MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Accepts input frequencies from 8kHz to 38.88MHz including 8kHz,
19.44MHz, 25MHz and 38.88MHz
Crystal interface optimized for a 27MHz, 10pF parallel
resonant crystal
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
Customized settings for jitter attenuation and reference tracking
using external loop filter connection
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
Absolute pull range: ±100ppm
Power supply noise rejection (PSNR): -95dB (typical)
RMS phase jitter @ 156.25MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.64ps (typical)
RMS phase jitter @ 155.52MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.64ps (typical)
RMS phase jitter @ 125MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.66ps (typical)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignments
XTAL_OUT
XTAL_IN
nCLK0
CLK0
V
CC
nCLK1
CLK1
V
CCX
•
•
•
•
24
V
EE
32 31 30 29 28 27 26 25
LF1
LF0
1
2
23 nQB
22
21
QB
V
CCO
ISET 3
V
EE
4
CLK_SEL
V
CC
5
6
20 nQA
19 QA
18
17
9
FB_SEL
LOR 7
V
EE
8
10 11 12 13 14 15 16
ODBSEL_1
ODBSEL_0
ODASEL_1
PDSEL_1
PDSEL_0
V
CC
V
CCA
V
EE
ODASEL_0
813N2532
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm ePad size
K Package
Top View
1
September 19, 2019
813N2532 Datasheet
Pin Description and Pin Characteristics Tables
Table 1. Pin Descriptions
Number
1, 2
3
4, 8, 18, 24
5
6, 12, 27
7
9
10,
11
13
14,
15
16,
17
19, 20
21
22, 23
25
26
28
29
30,
31
32
Name
LF1, LF0
ISET
V
EE
CLK_SEL
V
CC
LOR
FB_SEL
PDSEL_1,
PDSEL_0
V
CCA
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
QA, nQA
V
CCO
QB, nQB
nCLK1
CLK1
nCLK0
CLK0
XTAL_OUT,
XTAL_IN
V
CCX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Output
Input
Input
Power
Input
Input
Output
Power
Output
Input
Input
Input
Input
Input
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Description
Loop filter connection node pins. LF0 is the output. LF1 is the input.
Charge pump current setting pin.
Negative supply pins.
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Core supply pins.
Loss of reference indicator. LVCMOS/LVTTL interface levels.
Feedback divider select pin. LVCMOS/LVTTL interface levels.
See Table 3B.
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
Frequency select pins for Bank B output. See Table 3C.
LVCMOS/LVTTL interface levels.
Frequency select pins for Bank A output. See Table 3C.
LVCMOS/LVTTL interface levels.
Differential Bank A clock outputs. LVPECL interface levels.
Output supply pin.
Differential Bank B clock outputs. LVPECL interface levels.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply pin for the crystal oscillator.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
3
September 19, 2019
813N2532 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 2V
-0.5V to V
CC
+ 0.5V
50mA
100mA
33.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CCO
= V
CCX
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
V
CCX
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Crystal Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.29
3.135
3.135
Typical
3.3
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
3.465
312
29
Units
V
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCO
= V
CCX
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
CLK_SEL, CLK0,
ODASEL_[1:0],
ODBSEL_[1:0]
FB_SEL, PDSEL_[1:0]
Input
Low Current
CLK_SEL, CLK0,
ODASEL_[1:0],
ODBSEL_[1:0]
FB_SEL, PDSEL_[1:0]
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465, V
IN
= 0V
-10
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
10
Units
V
V
µA
µA
µA
µA
I
IH
I
IL
5
September 19, 2019
PCB Design
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